Publication List

Journals

  1. Xin Zhou, Koji Nakano, Yasuaki Ito, Efficient Implementation of FDFM Approach for Euclidean Algorithms on the FPGA, International Journal of Networking and Computing, to appear.
  2. Toru Fujita, Koji Nakano, and Yasuaki Ito, Fast Simulation of Conway's Game of Life using Bitwise Parallel Bulk Computation on a GPU, International Journal of Foundations of Computer Science, to appear.
  3. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Exhaustive Verification of the Collatz Conjecture, International Journal of Networking and Computing, to appear.
  4. Tatsuya Kawamoto, Xin Zhou, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, An FPGA implementation for a flexible-length-arithmetic processor employing the FDFM processor core approach, IEICE Transactions on Information and Systems, to appear.
  5. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Bulk Execution of Multiple-length Multiplication with Warp-synchronous Programming Technique, IEICE Transactions on Information and Systems, to appear.
  6. Hiroaki Koge, Takumi Honda, Toru Fujita, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Accelerating digital halftoning using the local exhaustive search on the GPU, Concurrency and Computation: Practice and Experience. (DOI), to appear.
  7. Yuji Takeuchi, Koji Nakano, Daisuke Takafuji, and Yasuaki Ito, A character art generator using the local exhaustive search, with GPU acceleration, International Journal of Parallel, Emergent and Distributed Systems, Vol. 31, No. 1, pp. 47–63, January 2016. (DOI)
  8. Toru Fujita, Koji Nakano, and Yasuaki Ito, Bulk execution of Euclidean algorithms on the CUDA-enabled GPU, International Journal of Networking and Computing (IJNC), Vol. 6, No. 1, pp. 42–63, January 2016. (DOI)
  9. Duhu Man, Koji Nakano, Yasuaki Ito, An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp.3063–3071, December 2014.(DOI)
  10. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation on the CUDA-enabled GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp. 3052–3062, December 2014.(DOI)
  11. Akihiro Uchida, Yasuaki Ito and Koji Nakano, Accelerating ant colony optimisation for the travelling salesman problem on the GPU, International Journal of Parallel, Emergent and Distributed Systems, Vol. 29, No. 4, pp. 401–420, 2014. (DOI)
  12. Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano, Implementations of the Hough Transform on the Embedded Multicore Processors, International Journal of Networking and Computing (IJNC), Vol. 4, No. 1, pp. 174–188, January 2014.
  13. Yasuaki Ito and Koji Nakano, A GPU Implementation of Dynamic Programming for the Optimal Polygon Triangulation, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2596–2603, December 2013. (DOI)
  14. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation Algorithms on the Discrete Memory Machine with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2617–2625, December 2013. (DOI)
  15. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating computation of Euclidean distance map using the GPU with Efficient memory access, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 5, pp. 383–406, 2013. (DOI)
  16. Yuki Ago, Yasuaki Ito, Koji Nakano, An FPGA implementation for neural networks with the FDFM processor core approach, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 4, pp. 308-320, 2013. (DOI)
  17. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles, International Journal of Networking and Computing (IJNC), Vol. 2, No. 1, pp. 269–290, July 2012.
  18. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Obtain Circuits with Synchronous RAMs, Journal of Communication and Computer, Vol. 9, No. 5, pp. 547-559, May 2012.
  19. Yasuaki Ito, Koji Nakano and Song Bo, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, International Journal of Networking and Computing (IJNC), Vol. 2, No. 1, pp. 79–96, January 2012.
  20. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones, IEICE Transactions on Information and Systems, Vol. E94-D, No. 12, pp. 2378–2388, December 2011. (DOI)
  21. Duhu Man, Yasuaki Ito, Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, International Journal on Foundations of Computer Science, Vol. 22, No. 5, pp. 1057–1071, August 2011. (DOI)
  22. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs, International Journal of Networking and Computing (IJNC), Vol. 1, No. 2, pp. 260–276, July 2011.
  23. Song Bo, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA, International Journal of Networking and Computing (IJNC), Vol. 1, No. 2, pp. 277–289, July 2011.
  24. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs, International Journal of Networking and Computing (IJNC), Vol. 1, No. 1, pp. 49–62, January 2011.
  25. Yasuaki Ito, Koji Nakano, Low-Latency Connected Component Labeling Using an FPGA, International Journal on Foundations of Computer Science, Vol. 21, No. 3, pp. 405–426, June 2010. (DOI)
  26. Yasuaki Ito, Koji Nakano, A New FM Screening Method to Generate Cluster-Dot Binary Images Using the Local Exhaustive Search with FPGA Acceleration, International Journal on Foundations of Computer Science, Vol. 19, No. 6, pp. 1373–1386, December 2008. (DOI)
  27. Yasuaki Ito, Koji Nakano, Youhei Yamagishi, Efficient Hardware Algorithms for N Choose K Counters Using the Bitonic Merger, International Journal on Foundations of Computer Science, Vol. 18, No. 3, pp. 517–528, June, 2007. (DOI)
  28. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, An Energy Efficient Leader Election Protocol for Radio Network with a Single Transceiver, IEICE Trans. on Fundamentals, Vol. E89-A, No. 5 pp. 1355–1361, May 2006. (DOI)
  29. Yasuaki Ito and Koji Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, International Journal of Foundations of Computer Science, Vol. 16, No. 1, pp. 89–104, February 2005. (DOI)
  30. Jacir L. Bordim, Oscar H. Ibarra, Yasuaki Ito, and Koji Nakano, Instance-Specific Solutions to Accelerate the CKY Parsing for Large Context-free Grammars, International Journal on Foundations of Computer Science, Vol 15, No. 2, pp. 403–416, April 2004. (DOI)
  31. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems, Vol. E86-D, No. 5, pp. 803–810, May 2003.

International Conferences

  1. Toru Fujita, Daigo Nishikori, Koji Nakano, Yasuaki Ito, Efficient GPU implementations for the Conway's Game of Life, Proc. International Symposium on Computing and Networking (CANDAR), pp. 11–20, December 2015. (DOI)
  2. Tatsuya Kawamoto, Yasuaki Ito, Koji Nakano, A flexible-length-arithmetic processor based on FDFM approach in FPGAs, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 364–370, December 2015. (DOI)
  3. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallelization Techniques for Error Diffusion with GPU Implementations, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 30–39, December 2015. (DOI)
  4. Lucas Saad, Jacir Bordim, Koji Nakano, Yasuaki Ito, A Fast Approximate String Matching Algorithm on GPU, Proc. International Symposium on Computing and Networking (CANDAR), pp. 188–192, December 2015. (DOI)
  5. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 96–102, December 2015. (DOI)
  6. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Fast LZW compression using a GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 303–308, December 2015. (DOI)
  7. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 228–237, 2015. (DOI)
  8. Xin Zhou, Koji Nakano, and Yasuaki Ito, Parallel FDFM Approach for Computing GCDs Using the FPGA, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 238–247, 2015. (DOI)
  9. Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito, Optimal Parallel Hardware K-Sorter and TopK-Sorter, with FPGA implementations, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 138–147, June 2015. (DOI)
  10. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, GPU-accelerated Digital Halftoning by the Local Exhaustive Search, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 82–87, June 2015. (DOI)
  11. Toru Fujita, Koji Nakano and Yasuaki Ito, Bulk GCD Computation Using a GPU to Break Weak RSA Keys, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 385–394, May 2015. (DOI)
  12. Koji Nakano and Yasuaki Ito, Optimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU implementation, Proc. of International Conference on Parallel, Distributed and Network-Based Processing, pp.626–634, March 2015. (DOI)
  13. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 447–452, December 2014. (DOI)
  14. Satoshi Okamoto, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Thorough Evaluation of GPU Shared Memory Load and Store Instructions, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 614–616, December 2014. (DOI)
  15. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, Proc. of International Conference on Parallel Processing, pp.251–250, September 2014. (DOI)
  16. Koji Nakano, Susumu Matsumae, Yasuaki Ito, Random Address Permute Shift Technique for the Shared Memory on GPUs, Proc. of International Conference on Parallel Processing Workshops, pp. 429–438, September 2014. (DOI)
  17. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8630), pp. 57–70, August 2014. (DOI)
  18. Takumi Honda, Yasuaki Ito and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 8630), pp. 483–496, August 2014. (DOI)
  19. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8631), pp. 178–191, August 2014. (DOI)
  20. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 762–770, May 2014. (DOI)
  21. Kazuya Tani, Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Bulk Execution of Oblivious Algorithms on the Unified Memory Machine, with GPU Implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 586–595, May 2014. (DOI)
  22. Koji Nakano, Susumu Matsumae and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 95–103, December 2013. (DOI)
  23. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 75–84, December 2013. (DOI)
  24. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 194–200, December 2013. (DOI)
  25. Kaoru Hashimoto, Yasuaki Ito and Koji Nakano, Template Matching using DSP slices on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 338–344, December 2013. (DOI)
  26. Ryosuke Nakamura, Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 639–641, December 2013. (DOI)
  27. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, in Proc. of 2013 International Conference on Parallel Processing (ICPP), pp. 1–10, October 2013. (DOI)
  28. Duhu Man, Koji Nakano and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 79–84, September 2013. (DOI)
  29. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 85–90, September 2013. (DOI)
  30. Yuki Ago, Koji Nakano and Yasuaki Ito, A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 91–96, September 2013. (DOI)
  31. Xin Zhou, Norihiro Tomagou, Yasuaki Ito and Koji Nakano, Efficient Hough Transform on the FPGA using DSP slices and Block RAMs, in Proc. of Workshop on Advances in Parallel and Distributed Computational Models (APDCM), pp. 771–778, May 2013. (DOI)
  32. Akihiro Uchida, Yasuaki Ito and Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of International Conference on Networking and Computing (ICNC), pp. 94–102, December 2012. (DOI)
  33. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, An Implementation of Conflict-Free Offline Permutation on the GPU, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 226–232, December 2012. (DOI)
  34. Edans Sandes, Jacir L. Bordim, Alba C. M. A. Melo and Yasuaki Ito, Record Route Elimination (RRE): An Energy-Efficient Broadcast Algorithm, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 247–253, December 2012. (DOI)
  35. Kazufumi Nishida, Koji Nakano, Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 7439), pp. 1–15, September 2012. (DOI)
  36. Duhu Man, Kenji Uda, Yasuaki Ito, and Koji Nakano, A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access, Proc. of International Conference on Networking and Computing (ICNC), pp. 68–76, December 2011. (DOI)
  37. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles, Proc. of International Conference on Networking and Computing (ICNC), pp. 77–86, December 2011. (DOI)
  38. Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of International Conference on Networking and Computing (ICNC), pp. 113–119, December 2011. (DOI)
  39. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of International Conference on Networking and Computing (ICNC), pp. 153–159, December 2011. (DOI)
  40. Yasuaki Ito, Kouhei Ogawa, and Koji Nakano, Fast Ellipse Detection Algorithm using Hough Transform on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 313–319, December 2011. (DOI)
  41. Kazufumi Nishida, Yasuaki Ito, and Koji Nakano, Accelerating the Dynamic Programming for the Matrix Chain Product on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 320–326, December 2011. (DOI)
  42. Bo Song, Yasuaki Ito, and Koji Nakano, CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models, pp. 527–536, May 2011. (DOI)
  43. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito, and Koji Nakano, Implementations of Parallel Computation of Euclidean Distance Map in Multicore Processors and GPUs, Proc. of International Conference on Networking and Computing (ICNC), pp. 120–127, November 2010. (DOI)
  44. Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito, An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA, Proc. of International Conference on Networking and Computing (ICNC), pp. 140–147, November 2010. (DOI)
  45. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits, Proc. of International Conference on Networking and Computing (ICNC), pp. 148–155, November 2010. (DOI)
  46. Kohei Ogawa, Yasuaki Ito, and Koji Nakano, Efficient Canny Edge Detection Using a GPU, Proc. of International Workshop on Advances in Networking and Computing (WANC), pp. 279–280, November 2010. (DOI)
  47. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2010.
  48. Duhu Man, Yasuaki Ito, and Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, Proc. of Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 506–511, December 2009. (DOI)
  49. Masaya Nakagawa, Duhu Man, Yasuaki Ito, and Koji Nakano, A Simple Parallel Convex Hull Algorithm for Sorted Points and the Performance Evaluation for the Multicore Processors, Proc. of Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 512–517, December 2009. (DOI)
  50. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of International Symposium on Parallel and Distributed Processing with Applications, pp. 63–70, August 2009. (DOI)
  51. Kimiharu Nishihata, Duhu Man, Yasuaki Ito, and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of the International Conference on Applications and Principles of Information Science (APIS), pp. 233–236, January 2009.
  52. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito, A Tiny Processing System for Education and Small Embedded Systems on the FPGAs, Proc. of Embedded Software Optimization (ESO), pp. 472–479, December 2008. (DOI)
  53. Koji Nakano, Yasuaki Ito, Processor, Assembler, and Compiler Design Education using an FPGA, Proc. of International Conference on Parallel and Distributed Systems (ICPADS), pp. 723–728, December 2008. (DOI)
  54. Yasuaki Ito, Koji Nakano, Optimized Component Labeling Algorithm for using in Medium Sized FPGAs, in Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies, pp. 171–176, December 2008. (DOI)
  55. Yasuaki Ito, Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM of International Parallel and Distributed Processing Symposium), April 2008. (DOI)
  56. Yasuaki Ito and Koji Nakano, Cluster-dot Screening by Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), March 2007.
  57. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Randomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver, Proc. of International Symposium on Parallel and Distributed Processing and Application(LNCS 4330), pp.246–256, December 2006. (DOI)
  58. Yasuaki Ito and Koji Nakano and Youhei Yamagishi, Efficient Hardware Algorithm for N Choose K Counters, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2006. (DOI)
  59. Y. Ito and K. Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2004. (DOI)
  60. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions to Accelerate the CKY parsing, Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms, pp. 72–78, June 2003.
  61. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY Parsing using FPGAs, Proc. of High Performance Computing (LNCS 2552), pp.41–51, December 2002.

International Conferences (non-refereed)

  1. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of LZW Decompression Using Block RAMs in the FPGA (Preliminary Version), The Fifth International Workshop on Networking, Computing, Systems, and Software, Sapporo, Hokkaido, December 2015.
  2. Toru Fujita, Koji Nakano and Yasuaki Ito. Bulk GCD Computation for Breaking Weak RSA Keys using a GPU, the 8th Annual Meeting of Asian Association for Algorithms and Computation (AAAC 2015), Miyajima, Hiroshima, May 2015.
  3. Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito. Optimal K-Sorter and TopK-Sorter using FPGAs, the 8th Annual Meeting of Asian Association for Algorithms and Computation (AAAC 2015), Miyajima, Hiroshima, May 2015.
  4. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, Implementations of Parallel Error Diffusion Optimized for GPU (Preliminary version), The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  5. Kaoru Hashimoto, Koji Nakano and Yasuaki Ito, Accelaration of the Smith-Waterman Algorithm with traceback on the FPGA, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  6. Masaaki Kuwada, Koji Nakano, Yasuaki Ito and Youhei Ishihara, Defect Inspection of an Arc Welded Bead Using a Support Vector Machine and a Neural Network, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  7. Ryosuke Sakai, Koji Nakano and Yasuaki Ito, Accelerating RSA encryption using GPUs, The Fourth International Workshop on Networking, Computing, Systems, and Software, Shizuoka, Shizuoka, December 2014.
  8. Yuki Yamamoto, Daisuke Takafuji, Yasuaki Ito, Koji Nakano and Tomoko Kashima, Sport support system using realtime audio feedback, The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  9. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, Fast image component labeling on the GPU (Preliminary version), The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  10. Daisuke Takafuji, Yasuaki Ito and Koji Nakano, Comparison of GPU Implementations of Row-wise and Column-wise Fundamental Algorithms, The Third International Workshop on Networking, Computing, Systems, and Software, Matsuyama, Ehime, December 2013.
  11. Xin Zhou, Yasuaki Ito and Koji Nakano, An FPGA Implementation of Hough Transform using DSP blocks and block RAMs, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.
  12. Yuki Ago, Yasuaki Ito and Koji Nakano, An Efficient Implementation of a Support Vector Machine in the FPGA, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.
  13. Norihiro Tomagou, Koji Nakano and Yasuaki Ito, An Implementation of Hough Transform on the GPU, The Second International Workshop on Networking, Computing, Systems, and Software, Naha, Okinawa, December 2012.

Domestic Conferences (non-refereed)

  1. 松本 直之, 周 昕, 中野 浩嗣, 伊藤 靖朗, FPGAを用いたハードウェアソーティングアルゴリズムの実装, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-103, pp. 37–42, Higashi-Hiroshima, Hiroshima, March 2016.
  2. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of LZW Decompression on the FPGA, IEICE Technical Report, Vol. 115, No. 447, IEICE-ICD2015-104, pp. 43–48, Higashi-Hiroshima, Hiroshima, March 2016.
  3. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 100–106, Kita-Nagoya, Aichi, September 2015.
  4. Toru Fujita, Daigo Nishikori, Koji Nakano and Yasuaki Ito, Efficient GPU implementations for the Conway’s Game of Life, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 169–178, Kita-Nagoya, Aichi, September 2015.
  5. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of The 11th Workshop on Theoretical Computer Science, pp. 179–188, Kita-Nagoya, Aichi, September 2015.
  6. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPU向け多倍長整数乗算, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-22, pp. 79–84, Beppu, Oita, August 2015.
  7. Shunji Funasaka, Yasuaki Ito, Koji Nakano, A Parallel Algorithm for LZW decompression, with GPU implementation, IEICE Technical Report, Vol. 115, No. 174, CPSY2015-24, pp. 91–96, Beppu, Oita, August 2015.
  8. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementations of Parallel Error Diffusion Optimized for GPU, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-57, pp. 19–24, Higashihiroshima, Hiroshima, November 2014.
  9. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-67, pp. 75–80, Higashihiroshima, Hiroshima, November 2014.
  10. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-68, pp. 81–86, Higashihiroshima, Hiroshima, November 2014.
  11. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-69, pp. 87–92, Higashihiroshima, Hiroshima, November 2014.
  12. 谷 和也, 中野 浩嗣, 伊藤 靖朗, GPUを用いた高スループット計算システムの実装, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-70, pp. 93–98, Higashihiroshima, Hiroshima, November 2014.
  13. 酒井 亮輔, 中野 浩嗣, 伊藤 靖朗, GPUを用いたRSA暗号の高速化, IEICE Technical Report, Vol. 114, No. 302, CPSY2014-71, pp. 99–104, Higashihiroshima, Hiroshima, November 2014.
  14. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-12, pp. 13–18, Niigata, Niigata, July 2014.
  15. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, IEICE Technical Report, Vol. 114, No. 155, CPSY2014-23, pp. 79–84, Niigata, Niigata, July 2014.
  16. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  17. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the Gradient-Based Hough Transform Using DSP Blocks and Block RAMs on the FPGA, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  18. Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, C2CU: A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  19. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, Random Address Permute-Shift Technique for the Shared Memory on GPUs, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  20. 高下 孔明, 伊藤 靖朗, 中野 浩嗣, GPUを用いたClipping-free Direct Binary Searchの高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  21. 本田 巧, 伊藤 靖朗, 中野 浩嗣, GPUを用いたコラッツ予想検証の高速化, 夏のLAシンポジウム2014, Iwakuni, Yamaguchi, July 2014.
  22. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-69, pp. 59–64, Kagoshima, Kagoshima, November 2013.
  23. Ryoshuke Nakamura and Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, IEICE Technical Report, Vol. 113, No. 324, CPSY2013-66, pp. 41–45, Kagoshima, Kagoshima, November 2013.
  24. Manduhu, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-41, pp. 13–18, Higashihiroshima, Hiroshima, November 2013.
  25. 蓬郷 典大, 中野 浩嗣, 伊藤 靖朗, GPUを用いたハフ変換の実装, IEICE Technical Report, Vol. 113, No. 282, CPSY2013-42, pp. 19–24, Higashihiroshima, Hiroshima, November 2013.
  26. Duhu Man, Koji Nakano, and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 15–20, Karatsu, Saga, September 2013.
  27. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, with Performance Evaluation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 21–30, Karatsu, Saga, September 2013.
  28. Koji Nakano, Susumu Matsumae, and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 83–91, Karatsu, Saga, September 2013.
  29. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 92–101, Karatsu, Saga, September 2013.
  30. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, Proc. of The 9th Workshop on Theoretical Computer Science, pp. 102–108, Karatsu, Saga, September 2013.
  31. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito, and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, IEICE Technical Report, Vol. 113, No. 169, CPSY2013-15, pp. 31–35, Kitakyushu, Fukuoka, August 2013.
  32. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Vol. 113, No. 169, CPSY2013-16, pp. 37–42, Kitakyushu, Fukuoka, August 2013.
  33. Kaoru Hashimoto, Yasuaki Ito, Koji Nakano, Template Matching using DSP slices on the FPGA, Vol. 113, No. 169, CPSY2013-17, pp. 43–48, Kitakyushu, Fukuoka, August 2013.
  34. Xin Zhou, Yasuaki Ito, and Koji Nakano, An implementation of Hough Transform Using DSP blocks and block RAMs on the FPGA, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-31, pp. 1–6, Higashihiroshima, Hiroshima, October 2012.
  35. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, A GPU Implementation of Conflict-Free Offline Permutation, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-35, pp. 25–30, Higashihiroshima, Hiroshima, October 2012.
  36. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient Implementation of Ant Colony Optimization for the Traveling Salesman Problem on the GPU, IEICE Technical Report, Vol. 112, No. 237, CPSY2012-36, pp. 31–36, Higashihiroshima, Hiroshima, October 2012.
  37. Xin Zhou, Yasuaki Ito, and Koji Nakano, Fast Hough Transform Using DSP blocks and block RAMs on the FPGA, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 27–33, Kobe, Hyogo, September 2012.
  38. Kazufumi Nishida, Koji Nakano, and Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 34–41, Kobe, Hyogo, September 2012.
  39. Akihiro Uchida, Yasuaki Ito, Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 42–50, Kobe, Hyogo, September 2012.
  40. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating Computation of Euclidean Distance Map using the GPU with Efficient Memory Access, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 51–63, Kobe, Hyogo, September 2012.
  41. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Implementation of Data Permutation on the GPU, Proc. of The 8th Workshop on Theoretical Computer Science, pp. 113–119, Kobe, Hyogo, September 2012.
  42. Yuki Agou, Yasuaki Ito, Koji Nakano, An FPGA Implementation for a 3-layer Perceptron with the FDFM Processor Core Approach, IEICE Technical Report, Vol. 112, No. 70, RECONF2012-8, pp. 43–48, Naha, Okinawa, May 2012.
  43. Yasuaki Ito, Koji Nakano, and Bo Song, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 103–113, Fukuma, Fukuoka, September 2011.
  44. Yuki Ago, Atsuo Inoue, Koji Nakano, Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 114–120, Fukuma, Fukuoka, September 2011.
  45. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of The 7th Workshop on Theoretical Computer Science, pp. 167–172, Fukuma, Fukuoka, September 2011.
  46. 伊藤靖朗, 中野浩嗣, FPGA のDSP ブロックを用いた高速計算, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 70–75, Nagashima, Mie, September 2010.
  47. Bo Song, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption using DSP slices and Block RAMs on the FPGA, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 76–84, Nagashima, Mie, September 2010.
  48. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 85–92, Nagashima, Mie, September 2010.
  49. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of Parallel Euclidean Distance Map Computation in Multicore Processors and GPUs, Proc. of The 6th Workshop on Theoretical Computer Science, pp. 93–100, Nagashima, Mie, September 2010.
  50. Yasuaki Ito and Koji Nakano, An Effcient Implementation of Exaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, IEICE Technical Report, Vol. 110, No. 32, RECONF2010-15, pp. 69–74, Nagasaki, May 2010.
  51. Yasuaki Ito and Koji Nakano, Component Labeling on the FPGA using Few Logic Elements, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-20, pp. 7–12, Utsunomiya, September 2009.
  52. Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto, An FPGA-based Tiny Processing System for Small Embedded System and Education, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-32, pp. 79–84, Utsunomiya, September 2009.
  53. Yasuaki Ito and Koji Nakano, An FPGA-based Architecture for Verifying Collatz Conjecture, IEICE Technical Report, Vol. 109, No. 198, RECONF2009-40, pp. 125–130, Utsunomiya, September 2009.
  54. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of The 5th Workshop on Theoretical Computer Sciences, pp.7–14, Hiroshima, September 2009.
  55. 中河雅弥,伊藤靖朗,中野浩嗣, 並列凸包計算アルゴリズムのマルチコアプロセッサ上での評価, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 67–68, Hiroshima, September 2009.
  56. Duhu Man , Yasuaki Ito and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of The 5th Workshop on Theoretical Computer Science, pp. 69–70, Hiroshima, September 2009.
  57. 伊藤靖朗, 同期ブロックRAMの非同期ブロックRAMへの変換について, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.151–157, Nagahama, Shiga, September 2008.
  58. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, and Yasuaki Ito, A Tiny Processing System for Education and Small Embedded System on the FPGA, Proc. of The 4th Workshop on Theoretical Computer Sciences, pp.135–142, Nagahama, Shiga, September 2008.
  59. Yasuaki Ito and Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, IEICE Technical Report, Vol. 107, No. 390, COMP2007-48, pp. 1–8, Hiroshima, December 2007.
  60. 伊藤靖朗, 中野浩嗣, FPGAを用いた二値画像のラベリング, Proc. of The 3rd Workshop on Theoretical Computer Sciences, pp.6–12, Mojiko, Fukuoka, September 2007.
  61. 伊藤 靖朗, 中野 浩嗣,山岸 洋平, n Choose k カウンタのハードウェア実装とその応用, Proc. of The 2nd Workshop on Theoretical Computer Sciences, pp.68–69, Seto, Aichi,September 2006.
  62. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた相関係数による画像のパターンマッチング, 2006年度 夏のLAシンポジウム, Hiroshima, August 2006.
  63. 伊藤 靖朗, 中野 浩嗣, FPGAを用いた大きな文法のCKYパージング, 平成16年度電気・情報関連学会中国支部第55回連合大会講演論文集, p.308, Ube, Yamaguchi, September 2004.
  64. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions for the CKY Parsing, 第1回 リコンフィギャラブル研究会 論文集, pp.27-33, Kumamoto, September 2003.
  65. Y. Ito, J. L. Bordim, and K. Nakano, Accelerating the CKY Parsing using FPGAs, Technical Report of IPSJ, AL2002-85 , pp. 35-42, Tokyo, July 2002.