Carry-lookahead adder

入出力

名前 入力・出力 ビット幅 説明
ain 入力 N
bin 入力 N
cin 入力 1 下位からの桁上がり
cout 出力 1 桁上がり
sout 出力 N 合計

コード

  • VerilogHDL
carry_lookahead_adder.v
module carry_lookahead_adder(ain, bin, cin, cout, sout);
  parameter N = 8;
 
  input [N-1:0] ain, bin;
  input cin;
  output reg cout;
  output reg [N-1:0] sout;
 
  reg [N:0] c;
  wire [N-1:0] g;
  wire [N-1:0] p;
 
  assign g = ain & bin;
  assign p = ain | bin;
 
  integer i;
  always@(ain or bin or cin or g or p or c)
  begin
    c[0] = cin;
    for(i=1;i<=N;i=i+1)
      c[i] = g[i-1] | (p[i-1] & c[i-1]);
 
    cout = c[N];
    sout = ain ^ bin ^ c[N-1:0];
  end
endmodule
  • VHDL
carry_lookahead_adder.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity carry_lookahead_adder is
  generic(N : integer := 8);
  port (ain, bin : in std_logic_vector(N-1 downto 0);
        cin : in std_logic;
        cout : out std_logic;
        sout : out std_logic_vector(N-1 downto 0) );
end carry_lookahead_adder;
 
architecture rtl of carry_lookahead_adder is
  signal p,g : std_logic_vector(N-1 downto 0);
begin
  g <= ain and bin;
  p <= ain or bin;
 
  process(ain, bin, cin, g, p)
    variable c : std_logic_vector(N downto 0);
    variable i : integer;
  begin
    c(0) := cin;
    for i in 1 to N loop
      c(i) := g(i-1) or (p(i-1) and c(i-1));
    end loop;
    cout <= c(N);
    sout <= ain xor bin xor c(N-1 downto 0);
  end process;
 
end rtl;

シミュレーション

  • テストベンチ(VerilogHDL)
carry_lookahead_adder_tb.v
`timescale 1ns / 1ps
module carry_lookahead_adder_tb;
  parameter N=8;
 
  reg [N-1:0] ain, bin;
  reg cin;
  wire cout;
  wire [N-1:0] sout;
 
  carry_lookahead_adder carry_lookahead_adder_d(
    .ain(ain), .bin(bin), .cin(cin),
    .cout(cout), .sout(sout));
 
  initial begin
    ain = 0; bin = 0; cin = 0;
    #100 ain = 12;  bin = 46; cin = 0;
    #100 ain = 12;  bin = 6;  cin = 1;
    #100 ain = 0;   bin = 4;  cin = 1;
    #100 ain = 112; bin = 9;  cin = 0;
    #100 ain = 12;  bin = 46; cin = 1;
    #100 ain = 255; bin = 0;  cin = 0;
    #100 ain = 255; bin = 0;  cin = 1;
    #100 ain = 0;   bin = 0;  cin = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
carry_lookahead_adder_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity carry_lookahead_adder_tb is
end carry_lookahead_adder_tb;
 
architecture rtl of carry_lookahead_adder_tb is
 
  component carry_lookahead_adder
    generic(N : integer := 8);
    port (ain, bin : in std_logic_vector(N-1 downto 0);
          cin : in std_logic;
          cout : out std_logic;
          sout : out std_logic_vector(N-1 downto 0) );
   end component;
 
  constant N : integer := 8;
 
  signal ain, bin, sout : std_logic_vector(N-1 downto 0);
  signal cin, cout : std_logic;
begin
  carry_lookahead_adder_d: carry_lookahead_adder
    generic map(N => N)
    port map(ain => ain, bin => bin, cin => cin,
             cout => cout, sout => sout);
  process
  begin
    ain <= X"00"; bin <= X"00"; cin <= '0';
    wait for 100 ns; ain <= X"0C"; bin <= X"01"; cin <= '0';
    wait for 100 ns; ain <= X"0C"; bin <= X"2E"; cin <= '1';
    wait for 100 ns; ain <= X"00"; bin <= X"06"; cin <= '1';
    wait for 100 ns; ain <= X"70"; bin <= X"09"; cin <= '0';
    wait for 100 ns; ain <= X"0C"; bin <= X"2E"; cin <= '1';
    wait for 100 ns; ain <= X"FF"; bin <= X"00"; cin <= '0';
    wait for 100 ns; ain <= X"FF"; bin <= X"00"; cin <= '1';
    wait for 100 ns; ain <= X"00"; bin <= X"00"; cin <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

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