デマルチプレクサ

入出力

名前 入力・出力 ビット幅 説明
din 入力 1
sel 入力 1 選択信号
aout 出力 1
bout 出力 1

真理値表

入力 出力
din sel aout bout
0 0 0 0
1 0 1 0
0 1 0 0
1 1 0 1

コード

  • VerilogHDL
demultiplexer.v
module demultiplexer(din, sel, aout, bout);
  input din, sel;
  output aout, bout;
 
  assign aout = (sel == 1'b0) ? din : 1'b0;
  assign bout = (sel == 1'b1) ? din : 1'b0;
endmodule
  • VHDL
demultiplexer.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity demultiplexer is
  port (din, sel : in std_logic;
        aout, bout : out std_logic );
end demultiplexer;
 
architecture demultiplexer_body of demultiplexer is
begin
  aout <= din when(sel = '0')else '0';
  bout <= din when(sel = '1')else '0';
end multiplexer_body;

シミュレーション

  • テストベンチ(VerilogHDL)
demultiplexer_tb.v
`timescale 1ns / 1ps
module demultiplexer_tb;
  reg din, sel;
  wire aout, bout;
 
  demultiplexer demultiplexer_d(.din(din), .sel(sel),
                                .aout(aout), .bout(bout));
 
  initial begin
    din = 0; sel = 0;
    #100 din = 0; sel = 0;
    #100 din = 0; sel = 1;
    #100 din = 1; sel = 0;
    #100 din = 1; sel = 1;
    #100 din = 0; sel = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
demultiplexer_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity demultiplexer_tb is
end demultiplexer_tb;
 
architecture demultiplexer_tb_body of demultiplexer_tb is
 
  component demultiplexer
  port( din, sel : in std_logic;
        aout, bout : out std_logic );
   end component;
 
  signal din, sel :  std_logic;
  signal aout, bout :  std_logic;
 
begin
  demultiplexer_d: demultiplexer port map(
    din => din,
    sel => sel,
    aout => aout,
    bout => bout
  );
 
  process
  begin
    din <= '0'; sel <= '0';
    wait for 100 ns; din <= '0'; sel <= '1';
    wait for 100 ns; din <= '1'; sel <= '0';
    wait for 100 ns; din <= '1'; sel <= '1';
    wait for 100 ns; din <= '0'; sel <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

関連項目