全加算器

入出力

名前 入力・出力 ビット幅 説明
ain 入力 1
bin 入力 1
cin 入力 1 下位からの桁上がり
cout 出力 1 桁上がり
sout 出力 1 合計

真理値表

入力 出力
ain bin cin cout sout
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

コード

  • VerilogHDL
full_adder.v
module full_adder(ain, bin, cin, cout, sout);
  input ain, bin, cin;
  output cout, sout;
 
  assign cout = (ain & bin) | (bin & cin) | (cin & ain);
  assign sout = ain ^ bin ^ cin;
endmodule
  • VHDL
full_adder.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity full_adder is
  port (ain, bin, cin : in std_logic;
        cout, sout : out std_logic );
end full_adder;
 
architecture full_adder_body of full_adder is
begin
  cout <= (ain and bin) or (bin and cin) or (cin and ain);
  sout <= ain xor bin xor cin;
end full_adder_body;

シミュレーション

  • テストベンチ(VerilogHDL)
full_adder_tb.v
`timescale 1ns / 1ps
module full_adder_tb;
  reg ain;
  reg bin;
  reg cin;
  wire cout;
  wire sout;
 
  full_adder full_adder_d (
    .ain(ain), 
    .bin(bin), 
    .cin(cin), 
    .cout(cout), 
    .sout(sout)
  );
 
  initial begin
    ain = 0; bin = 0; cin = 0;
    #100 ain = 0; bin = 0; cin = 1;
    #100 ain = 0; bin = 1; cin = 0;
    #100 ain = 0; bin = 1; cin = 1;
    #100 ain = 1; bin = 0; cin = 0;
    #100 ain = 1; bin = 0; cin = 1;
    #100 ain = 1; bin = 1; cin = 0;
    #100 ain = 1; bin = 1; cin = 1;
    #100 ain = 0; bin = 0; cin = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
full_adder_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity full_adder_tb is
end full_adder_tb;
 
architecture full_adder_tb_body of full_adder_tb is
 
  component full_adder
  port(
    ain, bin, cin : in std_logic;
    cout, sout : out std_logic
    );
   end component;
 
  signal ain, bin, cin :  std_logic;
  signal cout, sout :  std_logic;
begin
  full_adder_d: full_adder port map(
    ain => ain,
    bin => bin,
    cin => cin,
    cout => cout,
    sout => sout
  );
 
  process
  begin
    ain <= '0'; bin <= '0'; cin <= '0';
    wait for 100 ns; ain <= '0'; bin <= '0'; cin <= '1';
    wait for 100 ns; ain <= '0'; bin <= '1'; cin <= '0';
    wait for 100 ns; ain <= '0'; bin <= '1'; cin <= '1';
    wait for 100 ns; ain <= '1'; bin <= '0'; cin <= '0';
    wait for 100 ns; ain <= '1'; bin <= '0'; cin <= '1';
    wait for 100 ns; ain <= '1'; bin <= '1'; cin <= '0';
    wait for 100 ns; ain <= '1'; bin <= '1'; cin <= '1';
    wait for 100 ns; ain <= '0'; bin <= '0'; cin <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

関連項目