グレイコードカウンタ

入出力

名前 入力・出力 ビット幅 説明
clk 入力 1 同期信号
reset_n 入力 1 非同期リセット(不論理)
inc 入力 1 インクリメント
dout 出力 N 出力

真理値表

入力 出力
clk reset_n inc dout
0 0
クロックの立ち上がり 1 0 値を保持
クロックの立ち上がり 1 1 次のコード
クロックの立ち上がり以外 1 値を保持

クロックの立ち上がりはクロックの立ち上がり

コード

  • VerilogHDL
binary_counter.v
module binary_counter(clk, reset_n, inc, load, din, dout);
  parameter N = 4;
 
  input clk, reset_n, inc, load;
  input [N-1:0] din;
  output [N-1:0] dout;
  reg [N-1:0] count;
 
  always@(posedge clk or negedge reset_n)
    if(!reset_n)
      count <= 4'b0000;
    else if(inc)
      case(count)
        4'b0000: count <= 4'b0001;
        4'b0001: count <= 4'b0011;
        4'b0011: count <= 4'b0010;
        4'b0010: count <= 4'b0110;
        4'b0110: count <= 4'b0111;
        4'b0111: count <= 4'b0101;
        4'b0101: count <= 4'b0100;
        4'b0100: count <= 4'b1100;
        4'b1100: count <= 4'b1101;
        4'b1101: count <= 4'b1111;
        4'b1111: count <= 4'b1110;
        4'b1110: count <= 4'b1010;
        4'b1010: count <= 4'b1011;
        4'b1011: count <= 4'b1001;
        4'b1001: count <= 4'b1000;
        4'b1000: count <= 4'b0000;
        default: count <= 4'bxxxx;
      endcase
  assign dout = count;
endmodule
  • VHDL
binary_counter.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity binary_counter is
  generic(N : integer := 8);
  port (clk, reset_n, inc, load : in std_logic;
        din : in std_logic_vector(N-1 downto 0);
        dout : out std_logic_vector(N-1 downto 0) );
end binary_counter;
 
architecture binary_counter_body of binary_counter is
signal count : std_logic_vector(N-1 downto 0);
begin
  process(clk, reset_n)
  begin
    if(reset_n = '0') then
      count <= (others=>'0');
    elsif (clk'event and clk = '1') then
      if(inc = '1') then
        case count is
        when "0000" => count <= "0001";
        when "0001" => count <= "0011";
        when "0011" => count <= "0010";
        when "0010" => count <= "0110";
        when "0110" => count <= "0111";
        when "0111" => count <= "0101";
        when "0101" => count <= "0100";
        when "0100" => count <= "1100";
      end if;
    end if;
  end process;
 
  dout <= count;
end binary_counter_body;

シミュレーション

  • テストベンチ(VerilogHDL)
binary_counter_tb.v
`timescale 1ns / 1ps
module binary_counter_tb_v;
  parameter N = 8;
 
  reg clk, reset_n, inc, load;
  reg [N-1:0] din;
  wire [N-1:0] dout;
 
  binary_counter binary_counter_d(.clk(clk), .reset_n(reset_n),
                    .inc(inc), .load(load), .din(din), .dout(dout));
  defparam binary_counter_d.N = N;
 
  initial begin
    clk = 0;
    forever
      #50 clk = ~clk;
  end
 
  initial begin
    reset_n = 0; inc = 0; load = 0; din = 0;
    #100 reset_n = 1;
    #100 inc = 1;
    #400 inc = 0;
    #100 load = 1; din = 6;
    #100 din = 3;
    #100 inc = 1;
    #130 reset_n = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
binary_counter_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
entity binary_counter_tb is
  generic(N : integer := 8);
end binary_counter_tb;
 
architecture binary_counter_tb_body of binary_counter_tb is
 
  component binary_counter
    generic(N : integer := 8);
    port (clk, reset_n, inc, load : in std_logic;
          din : in std_logic_vector(N-1 downto 0);
          dout : out std_logic_vector(N-1 downto 0) );
  end component;
 
  signal clk :  std_logic := '0';
  signal reset_n, inc, load : std_logic;
  signal din : std_logic_vector(N-1 downto 0);
  signal dout : std_logic_vector(N-1 downto 0);
begin
 
  binary_counter_d: binary_counter port map(
    clk     => clk,
    reset_n => reset_n,
    inc     => inc,
    load    => load,
    din     => din,
    dout    => dout
  );
 
  process
  begin
    wait for 50 ns;
    clk <= not clk;
  end process;
 
  process
  begin
    reset_n <= '0'; inc <= '0'; load <= '0'; din <= (others=>'0');
    wait for 100 ns; reset_n <= '1';
    wait for 100 ns; inc <= '1';
    wait for 400 ns; inc <= '0';
    wait for 100 ns; load <= '1'; din <= CONV_std_logic_vector(6, N);
    wait for 100 ns; din <= CONV_std_logic_vector(3, N);
    wait for 100 ns; inc <= '1';
    wait for 130 ns; reset_n <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

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