半加算器

入出力

名前 入力・出力 ビット幅 説明
ain 入力 1
bin 入力 1
cout 出力 1 桁上がり
sout 出力 1 合計

真理値表

入力 出力
ain bin cout sout
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

コード

  • VerilogHDL
half_adder.v
module half_adder(ain, bin, cout, sout);
  input ain, bin;
  output cout, sout;
 
  assign cout = ain & bin;
  assign sout = ain ^ bin;
endmodule
  • VHDL
half_adder.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity half_adder is
  port (ain, bin : in std_logic;
        cout, sout : out std_logic
       );
end half_adder;
 
architecture half_adder_body of half_adder is
begin
  cout <= ain and bin;
  sout <= ain xor bin;
end half_adder_body;

シミュレーション

  • テストベンチ(VerilogHDL)
half_adder_tb.v
`timescale 1ns / 1ps
module half_adder_tb;
  reg ain;
  reg bin;
  wire cout;
  wire sout;
 
  half_adder half_adder_d(.ain(ain), .bin(bin), .cout(cout), .sout(sout));
 
  initial begin
    ain = 0; bin = 0;
    #100 ain = 0; bin = 1;
    #100 ain = 1; bin = 0;
    #100 ain = 1; bin = 1;
    #100 ain = 0; bin = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
half_adder_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity half_adder_tb is
end half_adder_tb;
 
architecture half_adder_tb_body of half_adder_tb is
 
  component half_adder
  port(
    ain, bin : in std_logic;
    cout, sout : out std_logic
    );
   end component;
 
  signal ain, bin :  std_logic;
  signal cout, sout :  std_logic;
 
begin
  half_adder_d: half_adder port map(
    ain => ain,
    bin => bin,
    cout => cout,
    sout => sout
  );
 
  process
  begin
    ain <= '0'; bin <= '0';
    wait for 100 ns; ain <= '0'; bin <= '1';
    wait for 100 ns; ain <= '1'; bin <= '0';
    wait for 100 ns; ain <= '1'; bin <= '1';
    wait for 100 ns; ain <= '0'; bin <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

関連項目