マルチプレクサ

入出力

名前 入力・出力 ビット幅 説明
ain 入力 1
bin 入力 1
sel 入力 1 選択信号
sout 出力 1

真理値表

入力 出力
ain bin sel sout
0 0 0
1 0 1
0 1 0
1 1 1

または

入力 出力
sel sout
0 ain
1 bin

コード

  • VerilogHDL
multiplexer.v
module multiplexer(ain, bin, sel, sout);
  input ain, bin;
  input sel;
  output sout;
 
  assign sout = (sel == 1'b0) ? ain : bin;
endmodule
  • VHDL
multiplexer.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity multiplexer is
  port (ain, bin, sel : in std_logic;
        sout : out std_logic );
end multiplexer;
 
architecture multiplexer_body of multiplexer is
begin
  sout <= ain when(sel = '0')else bin;
end multiplexer_body;

シミュレーション

  • テストベンチ(VerilogHDL)
multiplexer_tb.v
`timescale 1ns / 1ps
module multiplexer_tb;
  reg ain, bin, sel;
  wire sout;
 
  multiplexer multiplexer_d(.ain(ain), .bin(bin), .sel(sel), .sout(sout));
 
  initial begin
    ain = 0; bin = 0; sel = 0;
    #100 ain = 0; bin = 0; sel = 1;
    #100 ain = 0; bin = 1; sel = 0;
    #100 ain = 0; bin = 1; sel = 1;
    #100 ain = 1; bin = 0; sel = 0;
    #100 ain = 1; bin = 0; sel = 1;
    #100 ain = 1; bin = 1; sel = 0;
    #100 ain = 1; bin = 1; sel = 1;
    #100 ain = 0; bin = 0; sel = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
multiplexer_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity multiplexer_tb is
end multiplexer_tb;
 
architecture multiplexer_tb_body of multiplexer_tb is
 
  component multiplexer
  port( ain, bin, sel : in std_logic;
        sout : out std_logic );
   end component;
 
  signal ain, bin, sel :  std_logic;
  signal sout :  std_logic;
 
begin
  multiplexer_d: multiplexer port map(
    ain => ain,
    bin => bin,
    sel => sel,
    sout => sout
  );
 
  process
  begin
    ain <= '0'; bin <= '0'; sel <= '0';
    wait for 100 ns; ain <= '0'; bin <= '0'; sel <= '1';
    wait for 100 ns; ain <= '0'; bin <= '1'; sel <= '0';
    wait for 100 ns; ain <= '0'; bin <= '1'; sel <= '1';
    wait for 100 ns; ain <= '1'; bin <= '0'; sel <= '0';
    wait for 100 ns; ain <= '1'; bin <= '0'; sel <= '1';
    wait for 100 ns; ain <= '1'; bin <= '1'; sel <= '0';
    wait for 100 ns; ain <= '1'; bin <= '1'; sel <= '1';
    wait for 100 ns; ain <= '0'; bin <= '0'; sel <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

関連項目