乗算器

入出力

名前 入力・出力 ビット幅 説明
ain 入力 N
bin 入力 N
sout 出力 2N

コード

  • VerilogHDL
module multiplier(ain, bin, sout);
  parameter N = 8;
 
  input [N-1:0] ain, bin;
  output [2*N-1:0] sout;
 
  reg [2*N-1:0] sum;
  integer i;
 
  always@(ain or bin)
  begin
    sum = 0;
    for(i=0;i<N;i=i+1)
      sum = bin[i] ? sum+(ain<<i) : sum;
  end
 
  assign sout = sum;
endmodule

シミュレーション

  • テストベンチ(VerilogHDL)
`timescale 1ns / 1ps
module multiplier_tb;
  parameter N=8;
 
  reg [N-1:0] ain, bin;
  wire [2*N-1:0] sout;
 
  multiplier multiplier_d (
    .ain(ain), .bin(bin),
    .sout(sout)
  );
    defparam multiplier_d.N = N;
 
  initial begin
    ain = 0; bin = 0;
    #100 ain = 3;   bin = 4;
    #100 ain = 255; bin = 255;
    #100 ain = 100; bin = 128;
    #100 ain = 128; bin = 127;
    #100 ain = 255; bin = 1;
    #100 ain = 200; bin = 2;
    #100 ain = 0;   bin = 40;
    #100 ain = 0;   bin = 0;
  end
 
endmodule

関連項目