Nビット加算器

入出力

名前 入力・出力 ビット幅 説明
ain 入力 N
bin 入力 N
cin 入力 1 下位からの桁上がり
cout 出力 1 桁上がり
sout 出力 N 合計

コード

  • VerilogHDL
nbits_adder.v
module nbits_adder(ain, bin, cin, cout, sout);
  parameter N = 8;
 
  input [N-1:0] ain, bin;
  input cin;
  output cout;
  output [N-1:0] sout;
 
  assign {cout, sout} = ain + bin + cin;
endmodule
  • VHDL
nbits_adder.vhd
library	IEEE;
use IEEE.std_logic_1164.all;
 
entity nbits_adder is
  generic(N : integer := 8);
  port (ain, bin : in std_logic_vector(N-1 downto 0);
        cin : in std_logic;
        cout : out std_logic;
        sout : out std_logic_vector(N-1 downto 0) );
end nbits_adder;
 
architecture nbits_adder_body of nbits_adder is
  signal sum : std_logic_vector(N downto 0);
begin
  sum <= ('0' & ain) + ('0' & bin) + cin;
 
  cout <= sum(N);
  sout <= sum(N-1 downto 0);
end nbits_adder_body;

シミュレーション

  • テストベンチ(VerilogHDL)
nbits_adder_tb.vhd
`timescale 1ns / 1ps
module nbits_adder_tb;
  parameter N=8;
 
  reg [N-1:0] ain, bin;
  reg cin;
  wire cout;
  wire [N-1:0] sout;
 
  nbits_adder nbits_adder_d (
    .ain(ain), .bin(bin), .cin(cin),
    .cout(cout), .sout(sout)
  );
  defparam nbits_adder_d.N = N;
 
  initial begin
    ain = 0; bin = 0; cin = 0;
    #100 ain = 255; bin = 255; cin = 0;
    #100 ain = 255; bin = 255; cin = 1;
    #100 ain = 128; bin = 128; cin = 0;
    #100 ain = 128; bin = 127; cin = 1;
    #100 ain = 255; bin = 0; cin = 0;
    #100 ain = 255; bin = 0; cin = 1;
    #100 ain = 0; bin = 0; cin = 1;
    #100 ain = 0; bin = 0; cin = 0;
  end
 
endmodule
  • テストベンチ(VHDL)
nbits_adder_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
 
entity nbits_adder_tb is
end nbits_adder_tb;
 
architecture nbits_adder_tb_body of nbits_adder_tb is
 
  component nbits_adder
    generic(N : integer := 8);
    port (ain, bin : in std_logic_vector(N-1 downto 0);
          cin : in std_logic;
          cout : out std_logic;
          sout : out std_logic_vector(N-1 downto 0) );
   end component;
 
  constant N : integer := 8;
 
  signal ain, bin, sout : std_logic_vector(N-1 downto 0);
  signal cin, cout : std_logic;
begin
  nbits_adder_d: nbits_adder
    generic map(N => N)
    port map(ain => ain, bin => bin, cin => cin,
             cout => cout, sout => sout);
 
  process
  begin
    ain <= X"00"; bin <= X"00"; cin <= '0';
    wait for 100 ns; ain <= X"FF"; bin <= X"FF"; cin <= '0';
    wait for 100 ns; ain <= X"FF"; bin <= X"FF"; cin <= '1';
    wait for 100 ns; ain <= X"80"; bin <= X"80"; cin <= '0';
    wait for 100 ns; ain <= X"80"; bin <= X"7F"; cin <= '1';
    wait for 100 ns; ain <= X"FF"; bin <= X"00"; cin <= '0';
    wait for 100 ns; ain <= X"FF"; bin <= X"00"; cin <= '1';
    wait for 100 ns; ain <= X"00"; bin <= X"00"; cin <= '1';
    wait for 100 ns; ain <= X"00"; bin <= X"00"; cin <= '0';
    wait;
  end process;
 
end;
  • シミュレーション波形

関連項目