国際会議

  1. Toru Fujita, Daigo Nishikori, Koji Nakano, Yasuaki Ito, Efficient GPU implementations for the Conway's Game of Life, Proc. International Symposium on Computing and Networking (CANDAR), pp. 11–20, December 2015. (DOI)
  2. Tatsuya Kawamoto, Yasuaki Ito, Koji Nakano, A flexible-length-arithmetic processor based on FDFM approach in FPGAs, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 364–370, December 2015. (DOI)
  3. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallelization Techniques for Error Diffusion with GPU Implementations, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 30–39, December 2015. (DOI)
  4. Lucas Saad, Jacir Bordim, Koji Nakano, Yasuaki Ito, A Fast Approximate String Matching Algorithm on GPU, Proc. International Symposium on Computing and Networking (CANDAR), pp. 188–192, December 2015. (DOI)
  5. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 96–102, December 2015. (DOI)
  6. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Fast LZW compression using a GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 303–308, December 2015. (DOI)
  7. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, A Parallel Algorithm for LZW decompression, with GPU implementation, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 228–237, 2015. (DOI)
  8. Xin Zhou, Koji Nakano, and Yasuaki Ito, Parallel FDFM Approach for Computing GCDs Using the FPGA, Proc. of 11th International Conference of Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 238–247, 2015. (DOI)
  9. Naoyuki Matsumoto, Koji Nakano and Yasuaki Ito, Optimal Parallel Hardware K-Sorter and TopK-Sorter, with FPGA implementations, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 138–147, June 2015. (DOI)
  10. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, GPU-accelerated Digital Halftoning by the Local Exhaustive Search, Proc. of the 14th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 82–87, June 2015. (DOI)
  11. Toru Fujita, Koji Nakano and Yasuaki Ito, Bulk GCD Computation Using a GPU to Break Weak RSA Keys, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 385–394, May 2015. (DOI)
  12. Koji Nakano and Yasuaki Ito, Optimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU implementation, Proc. of International Conference on Parallel, Distributed and Network-Based Processing, pp.626–634, March 2015. (DOI)
  13. Xin Zhou, Yasuaki Ito, and Koji Nakano, An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 447–452, December 2014. (DOI)
  14. Satoshi Okamoto, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Thorough Evaluation of GPU Shared Memory Load and Store Instructions, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 614–616, December 2014. (DOI)
  15. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, Proc. of International Conference on Parallel Processing, pp.251–250, September 2014. (DOI)
  16. Koji Nakano, Susumu Matsumae, Yasuaki Ito, Random Address Permute Shift Technique for the Shared Memory on GPUs, Proc. of International Conference on Parallel Processing Workshops, pp. 429–438, September 2014. (DOI)
  17. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8630), pp. 57–70, August 2014. (DOI)
  18. Takumi Honda, Yasuaki Ito and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 8630), pp. 483–496, August 2014. (DOI)
  19. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8631), pp. 178–191, August 2014. (DOI)
  20. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 762–770, May 2014. (DOI)
  21. Kazuya Tani, Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Bulk Execution of Oblivious Algorithms on the Unified Memory Machine, with GPU Implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 586–595, May 2014. (DOI)
  22. Koji Nakano, Susumu Matsumae and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 95–103, December 2013. (DOI)
  23. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 75–84, December 2013. (DOI)
  24. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 194–200, December 2013. (DOI)
  25. Kaoru Hashimoto, Yasuaki Ito and Koji Nakano, Template Matching using DSP slices on the FPGA, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 338–344, December 2013. (DOI)
  26. Ryosuke Nakamura, Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, in Proc. of International Symposium on Computing and Networking (CANDAR), pp. 639–641, December 2013. (DOI)
  27. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, in Proc. of 2013 International Conference on Parallel Processing (ICPP), pp. 1–10, October 2013. (DOI)
  28. Duhu Man, Koji Nakano and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 79–84, September 2013. (DOI)
  29. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 85–90, September 2013. (DOI)
  30. Yuki Ago, Koji Nakano and Yasuaki Ito, A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 91–96, September 2013. (DOI)
  31. Xin Zhou, Norihiro Tomagou, Yasuaki Ito and Koji Nakano, Efficient Hough Transform on the FPGA using DSP slices and Block RAMs, in Proc. of Workshop on Advances in Parallel and Distributed Computational Models (APDCM), pp. 771–778, May 2013. (DOI)
  32. Akihiro Uchida, Yasuaki Ito and Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of International Conference on Networking and Computing (ICNC), pp. 94–102, December 2012. (DOI)
  33. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, An Implementation of Conflict-Free Offline Permutation on the GPU, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 226–232, December 2012. (DOI)
  34. Edans Sandes, Jacir L. Bordim, Alba C. M. A. Melo and Yasuaki Ito, Record Route Elimination (RRE): An Energy-Efficient Broadcast Algorithm, Proc. of International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 247–253, December 2012. (DOI)
  35. Kazufumi Nishida, Koji Nakano, Yasuaki Ito, Accelerating Dynamic Programming for the Optimal Polygon Triangulation on the GPU, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 7439), pp. 1–15, September 2012. (DOI)
  36. Duhu Man, Kenji Uda, Yasuaki Ito, and Koji Nakano, A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access, Proc. of International Conference on Networking and Computing (ICNC), pp. 68–76, December 2011. (DOI)
  37. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles, Proc. of International Conference on Networking and Computing (ICNC), pp. 77–86, December 2011. (DOI)
  38. Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of International Conference on Networking and Computing (ICNC), pp. 113–119, December 2011. (DOI)
  39. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of International Conference on Networking and Computing (ICNC), pp. 153–159, December 2011. (DOI)
  40. Yasuaki Ito, Kouhei Ogawa, and Koji Nakano, Fast Ellipse Detection Algorithm using Hough Transform on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 313–319, December 2011. (DOI)
  41. Kazufumi Nishida, Yasuaki Ito, and Koji Nakano, Accelerating the Dynamic Programming for the Matrix Chain Product on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors (CMPP), pp. 320–326, December 2011. (DOI)
  42. Bo Song, Yasuaki Ito, and Koji Nakano, CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models, pp. 527–536, May 2011. (DOI)
  43. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito, and Koji Nakano, Implementations of Parallel Computation of Euclidean Distance Map in Multicore Processors and GPUs, Proc. of International Conference on Networking and Computing (ICNC), pp. 120–127, November 2010. (DOI)
  44. Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito, An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA, Proc. of International Conference on Networking and Computing (ICNC), pp. 140–147, November 2010. (DOI)
  45. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits, Proc. of International Conference on Networking and Computing (ICNC), pp. 148–155, November 2010. (DOI)
  46. Kohei Ogawa, Yasuaki Ito, and Koji Nakano, Efficient Canny Edge Detection Using a GPU, Proc. of International Workshop on Advances in Networking and Computing (WANC), pp. 279–280, November 2010. (DOI)
  47. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2010.
  48. Duhu Man, Yasuaki Ito, and Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, Proc. of Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 506–511, December 2009. (DOI)
  49. Masaya Nakagawa, Duhu Man, Yasuaki Ito, and Koji Nakano, A Simple Parallel Convex Hull Algorithm for Sorted Points and the Performance Evaluation for the Multicore Processors, Proc. of Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 512–517, December 2009. (DOI)
  50. Yasuaki Ito and Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Conjecture, Proc. of International Symposium on Parallel and Distributed Processing with Applications, pp. 63–70, August 2009. (DOI)
  51. Kimiharu Nishihata, Duhu Man, Yasuaki Ito, and Koji Nakano, Parallel Sampling Sorting on the Multicore Processors, Proc. of the International Conference on Applications and Principles of Information Science (APIS), pp. 233–236, January 2009.
  52. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito, A Tiny Processing System for Education and Small Embedded Systems on the FPGAs, Proc. of Embedded Software Optimization (ESO), pp. 472–479, December 2008. (DOI)
  53. Koji Nakano, Yasuaki Ito, Processor, Assembler, and Compiler Design Education using an FPGA, Proc. of International Conference on Parallel and Distributed Systems (ICPADS), pp. 723–728, December 2008. (DOI)
  54. Yasuaki Ito, Koji Nakano, Optimized Component Labeling Algorithm for using in Medium Sized FPGAs, in Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies, pp. 171–176, December 2008. (DOI)
  55. Yasuaki Ito, Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM of International Parallel and Distributed Processing Symposium), April 2008. (DOI)
  56. Yasuaki Ito and Koji Nakano, Cluster-dot Screening by Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), March 2007.
  57. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Randomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver, Proc. of International Symposium on Parallel and Distributed Processing and Application(LNCS 4330), pp.246–256, December 2006. (DOI)
  58. Yasuaki Ito and Koji Nakano and Youhei Yamagishi, Efficient Hardware Algorithm for N Choose K Counters, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2006. (DOI)
  59. Y. Ito and K. Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2004. (DOI)
  60. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutions to Accelerate the CKY parsing, Proc. of International Conference on Engineering of Reconfigurable Systems and Algorithms, pp. 72–78, June 2003.
  61. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY Parsing using FPGAs, Proc. of High Performance Computing (LNCS 2552), pp.41–51, December 2002.