学術論文

  1. Xin Zhou, Koji Nakano, Yasuaki Ito, Efficient Implementation of FDFM Approach for Euclidean Algorithms on the FPGA, International Journal of Networking and Computing, to appear.
  2. Toru Fujita, Koji Nakano, and Yasuaki Ito, Fast Simulation of Conway's Game of Life using Bitwise Parallel Bulk Computation on a GPU, International Journal of Foundations of Computer Science, to appear.
  3. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Exhaustive Verification of the Collatz Conjecture, International Journal of Networking and Computing, to appear.
  4. Tatsuya Kawamoto, Xin Zhou, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, An FPGA implementation for a flexible-length-arithmetic processor employing the FDFM processor core approach, IEICE Transactions on Information and Systems, to appear.
  5. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Bulk Execution of Multiple-length Multiplication with Warp-synchronous Programming Technique, IEICE Transactions on Information and Systems, to appear.
  6. Hiroaki Koge, Takumi Honda, Toru Fujita, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Accelerating digital halftoning using the local exhaustive search on the GPU, Concurrency and Computation: Practice and Experience. (DOI), to appear.
  7. Yuji Takeuchi, Koji Nakano, Daisuke Takafuji, and Yasuaki Ito, A character art generator using the local exhaustive search, with GPU acceleration, International Journal of Parallel, Emergent and Distributed Systems, Vol. 31, No. 1, pp. 47–63, January 2016. (DOI)
  8. Toru Fujita, Koji Nakano, and Yasuaki Ito, Bulk execution of Euclidean algorithms on the CUDA-enabled GPU, International Journal of Networking and Computing (IJNC), Vol. 6, No. 1, pp. 42–63, January 2016. (DOI)
  9. Duhu Man, Koji Nakano, Yasuaki Ito, An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp.3063–3071, December 2014.(DOI)
  10. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation on the CUDA-enabled GPU, IEICE Transactions on Information and Systems, Vol. E97-D, No.12, pp. 3052–3062, December 2014.(DOI)
  11. Akihiro Uchida, Yasuaki Ito and Koji Nakano, Accelerating ant colony optimisation for the travelling salesman problem on the GPU, International Journal of Parallel, Emergent and Distributed Systems, Vol. 29, No. 4, pp. 401–420, 2014. (DOI)
  12. Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano, Implementations of the Hough Transform on the Embedded Multicore Processors, International Journal of Networking and Computing (IJNC), Vol. 4, No. 1, pp. 174–188, January 2014.
  13. Yasuaki Ito and Koji Nakano, A GPU Implementation of Dynamic Programming for the Optimal Polygon Triangulation, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2596–2603, December 2013. (DOI)
  14. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation Algorithms on the Discrete Memory Machine with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2617–2625, December 2013. (DOI)
  15. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating computation of Euclidean distance map using the GPU with Efficient memory access, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 5, pp. 383–406, 2013. (DOI)
  16. Yuki Ago, Yasuaki Ito, Koji Nakano, An FPGA implementation for neural networks with the FDFM processor core approach, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 4, pp. 308-320, 2013. (DOI)
  17. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles, International Journal of Networking and Computing (IJNC), Vol. 2, No. 1, pp. 269–290, July 2012.
  18. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Obtain Circuits with Synchronous RAMs, Journal of Communication and Computer, Vol. 9, No. 5, pp. 547-559, May 2012.
  19. Yasuaki Ito, Koji Nakano and Song Bo, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, International Journal of Networking and Computing (IJNC), Vol. 2, No. 1, pp. 79–96, January 2012.
  20. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones, IEICE Transactions on Information and Systems, Vol. E94-D, No. 12, pp. 2378–2388, December 2011. (DOI)
  21. Duhu Man, Yasuaki Ito, Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard qsort, International Journal on Foundations of Computer Science, Vol. 22, No. 5, pp. 1057–1071, August 2011. (DOI)
  22. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito and Koji Nakano, Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs, International Journal of Networking and Computing (IJNC), Vol. 1, No. 2, pp. 260–276, July 2011.
  23. Song Bo, Kensuke Kawakami, Koji Nakano and Yasuaki Ito, An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA, International Journal of Networking and Computing (IJNC), Vol. 1, No. 2, pp. 277–289, July 2011.
  24. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs, International Journal of Networking and Computing (IJNC), Vol. 1, No. 1, pp. 49–62, January 2011.
  25. Yasuaki Ito, Koji Nakano, Low-Latency Connected Component Labeling Using an FPGA, International Journal on Foundations of Computer Science, Vol. 21, No. 3, pp. 405–426, June 2010. (DOI)
  26. Yasuaki Ito, Koji Nakano, A New FM Screening Method to Generate Cluster-Dot Binary Images Using the Local Exhaustive Search with FPGA Acceleration, International Journal on Foundations of Computer Science, Vol. 19, No. 6, pp. 1373–1386, December 2008. (DOI)
  27. Yasuaki Ito, Koji Nakano, Youhei Yamagishi, Efficient Hardware Algorithms for N Choose K Counters Using the Bitonic Merger, International Journal on Foundations of Computer Science, Vol. 18, No. 3, pp. 517–528, June, 2007. (DOI)
  28. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, An Energy Efficient Leader Election Protocol for Radio Network with a Single Transceiver, IEICE Trans. on Fundamentals, Vol. E89-A, No. 5 pp. 1355–1361, May 2006. (DOI)
  29. Yasuaki Ito and Koji Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, International Journal of Foundations of Computer Science, Vol. 16, No. 1, pp. 89–104, February 2005. (DOI)
  30. Jacir L. Bordim, Oscar H. Ibarra, Yasuaki Ito, and Koji Nakano, Instance-Specific Solutions to Accelerate the CKY Parsing for Large Context-free Grammars, International Journal on Foundations of Computer Science, Vol 15, No. 2, pp. 403–416, April 2004. (DOI)
  31. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems, Vol. E86-D, No. 5, pp. 803–810, May 2003.