[[en:publication]]
 
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Publication List

Journal Papers

  1. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, Efficient Parallel Implementations to Compute the Diameter of a Graph, Concurrency and Computation: Practice and Experience, to appear.(Link)
  2. Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, Yasuaki Ito, Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA, Concurrency and Computation: Practice and Experience, to appear. (Link)
  3. Kohei Yamashita, Yasuaki Ito, Koji Nakano, Bulk execution of the dynamic programming for the optimal polygon triangulation problem on the GPU, Concurrency and Computation: Practice and Experience, Vol. 31, No. 19, e4947, September, 2019. (Link)
  4. Hiroki Tokura, Toru Fujita, Koji Nakano, Yasuaki Ito, and Jacir L. Bordim, Almost optimal column-wise prefix-sum computation on the GPU, The Journal of Supercomputing, Vol. 74, No. 4, pp. 1510–1521, April 2018. (Link)
  5. Toru Fujita, Koji Nakano, Yasuaki Ito, Daisuke Takafuji, An Efficient GPU Implementation of CKY Parsing Using the Bitwise Parallel Bulk Computation Technique. IEICE Transactions on Information and systems, Vol. E100-D, No. 12, pp.. 2857-2865, Dec. 2017. (Link)
  6. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Adaptive loss-less data compression method optimized for GPU decompression. Concurrency and Computation: Practice and Experience, Vol. 29, No. 24, Aug. 2017. (PDF)
  7. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota, Masami Saeki, An Efficient GPU Implementation of Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices. IJNC Vol. 7, No. 2, pp. 227-247, July 2017. (IJNC)
  8. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Exhaustive Verification of the Collatz Conjecture, International Journal of Networking and Computing, Vol. 7, No.1, pp. 69–85, January 2017 (IJNC).
  9. Daisuke Takafuji, Koji Nakano, Yasuaki Ito, and Jacir Bordim, C2CU: a CUDA C program generator for bulk execution of a sequential algorithm, Concurrency and Computation: Practice and Experience, Vol. 29, No. 17, Dec, 2016. (Link)
  10. Toru Fujita, Koji Nakano, and Yasuaki Ito, Fast Simulation of Conway's Game of Life using Bitwise Parallel Bulk Computation on a GPU, International Journal of Foundations of Computer Science, Volume 27, No. 8, 981-1003, Dec. 2016(PDF).
  11. Hiroaki Kouge, Takumi Honda, Toru Fujita, Yasuaki Ito, Koji Nakano, and Jacir L. Bordim, Accelerating digital halftoning using the local exhaustive search on the GPU, Concurrency and Computation: Practice and Experience, Vol.29, No. 2, e3781, Feb. 2016. (Link)
  12. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, Fully Parallelized LZW decompression for CUDA-enabled GPUs, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2986–2994, December 2016 (PDF).
  13. Lucas Saad Nogueira Numes, Jacir Luiz Bordim, Koji Nakano, and Yasuaki Ito, A Memory-access-efficient Implementation for Computing the Approximate String Matching Algorithm on GPUs, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2995–3003, December 2016. (Link)
  14. Tatsuya Kawamoto, Xin Zhou, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, An FPGA implementation for a flexible-length-arithmetic processor employing the FDFM processor core approach, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 2901–2910, December 2016. (Link)
  15. Takumi Honda, Yasuaki Ito, and Koji Nakano, GPU-accelerated Bulk Execution of Multiple-length Multiplication with Warp-synchronous Programming Technique, IEICE Transactions on Information and Systems, Vol. E99-D, No. 12, pp. 3004–3012, December 2016. (Link)
  16. Xin Zhou, Koji Nakano, Yasuaki Ito, Efficient Implementation of FDFM Approach for Euclidean Algorithms on the FPGA, International Journal of Networking and Computing, Vol. 6, No. 2, pp. 420–435, July 2016.(IJNC)
  17. Toru Fujita, Koji Nakano, Yasuaki Ito, Bulk execution of Euclidean algorithms on the CUDA-enabled GPU. International Journal of Networking and Computing, Vol. 6, No. 1, pp. 42-63, Jan., 2016 (LINK).
  18. Yuji Takeuchi, Koji Nakano, Daisuke Takafuji, Yasuaki Ito, A character art generator using the local exhaustive search, with GPU acceleration. International Journal of Parallel, Emergent and Distributed Systems, Vol. 31 No. 1, Pages 47-63, Jan. 2016 (PDF).
  19. Lucas de Melo Guimarães, Jacir Luiz Bordim, Koji Nakano, Using Pulse/Tone Signals as an Alternative to Boost Channel Reservation on Directional Communications. IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences, Vol. 98-A, No. 8, pp. 1647-1656, Aug, 2015.
  20. Duhu MAN, Koji NAKANO, Yasuaki ITO, An Optimal Implementation of the Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation on the GPU, IEICE TRANSACTIONS on Information and Systems, Vol.E97-D, No.12, pp.3063-3071, Dec. 2014 (PDF).
  21. Akihiko KASAGI, Koji NAKANO, Yasuaki ITO, Offline Permutation on the CUDA-enabled GPU, IEICE TRANSACTIONS on Information and Systems, Vol.E97-D, No.12, pp.3052-3062, 2014 (PDF).
  22. Akihiro Uchida, Yasuaki Ito, Koji Nakano, Accelerating ant colony optimisation for the travelling salesman problem on the GPU, International Journal of Parallel, Emergent and Distributed Systems, Volume 29, Issue 4, pp. 401-420, 2014 (PDF).
  23. Koji Nakano, Asynchronous Memory Machine Models with Barrier Synchronization, IEICE TRANSACTIONS on Information and Systems, Volume E97-D, No.3, pp.431-441, March 2014, (PDF).
  24. Koji Nakano, Optimal implementations of the approximate string matching and the approximate discrete signal matching on the memory machine models, International Journal of Parallel, Emergent and Distributed Systems, Volume 29, Issue 2, pp. 104-118, 2014 (PDF).
  25. Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano, Implementations of the Hough Transform on the Embedded Multicore Processors, International Journal of Networking and Computing, Vol. 4, No. 1, pp. 174–188, January 2014, (PDF).
  26. Koji Nakano, Simple memory machine models for GPUs, International Journal of Parallel, Emergent and Distributed Systems, Vol. 29, No. 1 pp. 17–37, 2014, (PDF).
  27. Yasuaki Ito and Koji Nakano, A GPU Implementation of Dynamic Programming for the Optimal Polygon Triangulation, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2596–2603, December 2013, (PDF)
  28. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, Offline Permutation Algorithms on the Discrete Memory Machine with Performance Evaluation on the GPU, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2617–2625, December 2013, (PDF).
  29. Koji Nakano, Optimal Parallel Algorithms for Computing the Sum, the Prefix-sums, and the Summed Area Table on the Memory Machine Models, IEICE Transactions on Information and Systems, Vol. E96-D, No. 12, pp. 2626–2634, December 2013, (PDF).
  30. Duhu Man, Kenji Uda, Yasuaki Ito and Koji Nakano, Accelerating computation of Euclidean distance map using the GPU with Efficient memory access, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 5, pp. 383–406, 2013.(PDF)
  31. Yuki Ago, Yasuaki Ito, Koji Nakano, An FPGA implementation for neural networks with the FDFM processor core approach, International Journal of Parallel, Emergent and Distributed Systems, Vol. 28, No. 4, pp. 308–320, 2013. (PDF)
  32. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles, International Journal of Networking and Computing, Vol. 2, No. 2, pp. 269-290, July 2012. (PDF)
  33. Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito, An Algorithm to Obtain Circuits with Synchronous RAMs, Journal of Communication and Computer, Volume 9, Number 5, pp. 547-559, May 2012.(PDF)
  34. Yasuaki Ito, Koji Nakano and Song Bo, The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption, International Journal of Networking and Computing, Vol. 2, No. 1, pp. 79–96, January 2012. (PDF)
  35. Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito, A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones, IEICE Transactions on Information and Systems Vol.E94-D No.12 pp.2378-2388, Dec 2011. (PDF)
  36. Duhu Man, Yasuaki Ito, Koji Nakano, An Efficient Parallel Sorting Algorithm Compatible with the Standard Qsort, International Journal on Foundations of Computer Science, pp. 1057–1072, Vol. 22, No. 5, Aug 2011. (PDF)
  37. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito, Koji Nakano, Implementations of a Parallel Algorithm for Computing Euclidean Distance Map in Multicore Processors and GPUs International Journal of Networking and Computing, Vol. 1, No.2, pp. 260–276, July, 2011. (PDF)
  38. Song Bo, Kensuke Kawakami, Koji Nakano, Yasuaki Ito An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA International Journal of Networking and Computing, Vol. 1, No.2, pp. 277–289, July, 2011. (PDF)
  39. Yudi Adityawarman, Arata Kaneko, Koji Nakano, Naokazu Taniguchi, Katsuaki Komai, Xinyu Guo, Noriaki Gohda, Reciprocal sound transmission measurement of mean current and temperature variations in the central part (Aki-nada) of the Seto Inland Sea, Japan JOURNAL OF OCEANOGRAPHY, Vol. 67, No. 2, pp. 173-182, Apr. 2011.
  40. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs International Journal of Networking and Computing, Vol. 1, No.1, pp. 49–62, Jan 2011. (PDF)
  41. Jacir L. Bordim and Koji Nakano, Deafness Resilient MAC Protocol for Directional Communications, IEICE Trans. on Information & Systems, Vol. E93-D No. 12, pp.3243-3250, Dec, 2010. (PDF)
  42. Xia Zhuge and Koji Nakano, Image Hiding Algorithms Based on Halftoning Technique, Journal of Communication and Computer, Vol. 7, No, 11, pp. 58-66, November 2010. (PDF)
  43. Xia Zhuge and Koji Nakano, Halftoning via Error Diffusion using Circular Dot-overlap Model, International Journal of Digital Content Technology and its Applications, Vol. 4, No, 6, pp. 8-17, Sept 2010. (PDF)
  44. Yasuaki Ito and Koji Nakano, Low-latency Connected Component Labeling Using an FPGA, International Journal on Foundations of Computer Science, Vol.21, No. 3. pp. 405-425, June 2010. (PDF)
  45. Xia Zhuge, Koji Nakano, Halftoning based algorithms for image hiding, Journal of Communication and Computer, Vol 6, No. 9, pp. 39–45, Sept. 2009.
  46. Xia Zhuge, Koji Nakano, Clipping-Free Halftoning and Multitoning Using the Direct Binary Search, IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.4, pp.1192-1201, Apr 2009. (PDF)
  47. Yasuaki Ito, Koji Nakano, A New FM Screening Method to Generate Cluster-Dot Binary Images Using the Local Exhaustive Search with FPGA Acceleration, International Journal on Foundations of Computer Science, Vol. 19, No. 6, pp. 1373-1386, Dec 2008. (PDF)
  48. Koji Nakano, Near Optimal Randomized Initialization on the 1-Dimensinal Reconfigurable Mesh, International Journal of Principles and Applications in Information Science and Technology, Vol. 1, No. 1, pp.53–64, Dec, 2007.
  49. Yasuaki Ito, Koij Nakano, Youhei Yamagishi, Efficient Hardware Algorithms for N Choose K Counters Using the Bitonic Merger, International Journal on Foundations of Computer Science, Vol. 18, No.3, pp.517-528, June 2007. (PDF)
  50. Koji Nakano, An Energy Efficient Ranking Protocol for Radio Networks, IEICE Trans. on Fundamentals, Vol. E89-A, No. 5, pp. 1346-1354, May 2006.
  51. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, An Energy Efficient Leader Election Protocol for Radio Network with a Single Transceiver, IEICE Trans. on Fundamentals, Vol. E89-A, No.5, pp. 1355-1361, May 2006. (PDF)
  52. Koji Nakano, and Youhei Yamagishi, Hardware n Choose k Counters with Applications to the Partial Exhaustive Search, IEICE Trans. on Information & Systems, Vol. E-88-D, No. 7, pp. 1350-1359, July 2005. (PDF)
  53. Yasuaki Ito, and Koji Nakano, FM Screening by the Local Exhaustive Search with Hardware Acceleration, International Journal on Foundations of Computer Science, Vo.16, No.1, pp. 89-104, Feb. 2005. (PDF)
  54. Jacir L Bordim, Oscar H. Ibarra, Yasuaki Ito, and Koji Nakano, Instance-Specific Solutions to Accelerate the CKY Parsing for Large Contex-free Grammars, International Journal on Foundations of Computer Science, Vol 15, No.2, pp.403-416, April 2004. (PDF)
  55. Koji Nakano, Time and Energy Optimal List Ranking Algorithms on the k-Channel Broadcast Communication Model with no Collision Detection, International Journal on Foundations of Computer Science, Vol. 15, No.1, pp.73–88, Feb. 2004. (PDF)
  56. Mark Daley, Oscar H. Ibarra, Lila Kari, Ian McQuillan, Koji Nakano, The LD and DLAD Bio-Operations on Formal Languages, Journal of Automata, Languages and Combinatorics, Vol 8, No.3, pp.477-498, 2003.
  57. Rong Lin, Koji Nakano, Stephan Olariu, and Albert Zomaya An Efficient Parallel Prefix Architecture with Domino Logic, IEEE Trans. on Parallel and Distributed Systems, Vol 14, No.9, pp.922-931, Sept, 2003.
  58. Jacir L Bordim, Koji Nakano, Hong Shen, Sorting on Single-Channel Wireless Sensor Networks, International Journal on Foundations of Computer Science, Vo. 14, No.3, fpp.391–403, June 2003.
  59. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelarating the CKY parsing using FPGAs, IEICE Transactions on Information and Systems, Vol. E86-D, No.5, pp.803-810, May, 2003. (PDF)
  60. Koji Nakano, Etsuko Takamichi, An Image Retrieval System Using FPGAs, IEICE Transactions on Information and Systems, Vol. E86-D, No.5, pp.811-818, May, 2003. (PDF)
  61. Jacir, L. Bordim, Jiangtao Cui, and Koji Nakano, Randomized Time- and Energy-Optimal Routing in Single-Hop Single-Channel Radio Networks, IEICE Transactions on Fundamentals, Vol. E86-A, No.5, pp. 1103–1112, May, 2003.
  62. Koji Nakano, Linear Layout of Generalized Hypercubes, International Journal on Foundations of Computer Science, Vol.14, No. 1, pp.137–156, Feb. 2003.(PDF)
  63. Koji Nakano, Stephan Olariu, and Albert Zomaya, Energy-Efficient Routing in the Broadcast Communication Model, IEEE Trans. on Parallel and Distributed Systems, Vol. 13, No. 2, pp. 1201-1210, Dec. 2002.
  64. Koji Nakano, Stephan Olariu, and Albert Zomaya, A Time-Optimal Solution for the Path Cover Problems on Cographs, Theoretical Computer Science, Vol. 290/3 pp. 1541-1556, Nov., 2002
  65. R. S. Bhuvaneswaran, Jacir, L. Bordim, Jiangtao Cui, and Koji Nakano. Fundamental Protocols for Wireless Sensor Networks, IEICE Trans. on Fundamentals, Vol. E85-A, pp. 2479–2488, No.11, Nov., 2002.
  66. Jacir L. Bordim, Frank Hsu, Koji Nakano, Identifying Faulty Nodes in Wireles Sensor Networks, Journal of Interconnection Networks, Vol. 3, No.3, pp.197–211, Sept. 2002.
  67. Jacir L. Bordim, Tatsuya Hayashi, and Koji Nakano A tool for Algorithm Visualization on the Reconfigurable Mesh, VLSI design, Vol.14, No.3, pp. 239–248, May, 2002.
  68. Koji Nakano and Stephan Olariu, Uniform Leader Election Protocols in Radio Networks, IEEE Trans. on Parallel and Distributed Systems, Vol. 13, No.5, pp.516–526, May, 2002.
  69. Jacir L. Bordim, Jiangtao Cui, Naohiro Ishii, and Koji Nakano, Doubly-logarithmic energy-efficient initializaiton protocol for single-hop radio network, IEICE Trans. on Fundamentals, Vol. E85-A, No.5, 967-976, May, 2002.
  70. R. S. Bhuvaneswaran, Jacir L. Bordim, Jiangtao Cui, Naohiro Ishii, and Koji Nakano, An Energy-efficient Initialization Protocol for Wireless Sensor Networks, IEICE Trans. on Fundamentals, Vol. E85-A, No.2, 447-454, Feb., 2002.
  71. Venkatavasu Bokka, Koji Nakano, Stephan Olariu, James L. Schwing, Larry Wilson Optimal Algorithms for the Multiple Query Problem on the Reconfigurable Mesh with Applications, IEEE Trans. on Parallel and Distributed Systems, Vol. 12, No.9, 875–887, Sept. 2001.
  72. Koji Nakano, Stephan Olariu, Albert Y. Zomaya, Energy-Efficient Permutation Routing Protocols in Radio Networks, IEEE Trans. on Parallel and Distributed Systems, Vol. 12, No.6, 544-557, June, 2001.
  73. Jacir L. Bordim, Jiangtao Cui, Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Energy-Efficient Initialization Protocols for Ad-hoc Radio Networks, IEICE Trans. Fundamentals, Vol.E-83-A. No.9, pp. 1796–1803, Sept. 2000
  74. Koji Nakano, and Stephan Olariu, Energy-Efficient Initialization Protocols for Single-Hop Radio Networks with no Collision Detection, IEEE Trans. on Parallel and Distributed Systems, Vol. 11, No. 8, pp. 851–863, Aug. 2000.
  75. Rong Lin, Koji Nakano, Stephan Olariu, M. C. Pinotti, James L. Schwing, and Albert Y. Zomaya, Scalable Hardware-Algorithms for Binary Prefix Sums, IEEE Trans. on Parallel and Distributed Systems, Vol. 11, No. 8, pp. 838–850, Aug. 2000.
  76. Koji Nakano and Stephan Olariu, Randomized Initialization Protocols for Ad-Hoc Networks, IEEE Trans. on Parallel and Distributed Systems, Vol. 11, No. 7, pp. 749–759, Jul. 2000.
  77. Koji Nakano, Stephan Olariu, and James L. Schwing, Broadcast-Efficient Protocols for Mobile Radio Networks, IEEE Tran. on Parallel and Distributed Systems, Vol. 10, No.12, pp.1276–1289, Dec 1999.
  78. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Optimal Parallel Algorithms for Proximate Points, with Applications, IEEE Trans. on Parallel and Distributed Systems, Vol. 9, No. 12 pp. 1153–1166, Dec 1998.
  79. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, An O((log log n)^2) Time Convex Hull Algorithm on Reconfigurable Meshes IEEE Trans. on Parallel and Distributed Systems, Vol. 9, No. 12 pp. 1167–1179, Dec 1998.
  80. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Efficient List Ranking on the Reconfigurable Mesh, with Applications, Theory of Computing Systems, Vol. 31, 593–611, 1998.
  81. Koji Nakano, and Stephan Olariu, An Efficient Algorithm for Row Minima Computations on Basic Recofigurable Meshes, IEEE Trans. on Parallel and Distributed Systems, pp.561–569, Jun, 1998.
  82. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Work-Time Optimal k-merge Algorithms on the PRAM, IEEE Trans. on Parallel and Distributed Systems, Vol. 9, No.3, pp. 275–282, Mar, 1998.
  83. Koji Nakano and Koichi Wada, Integer Summing Algorithms on Reconfigurable Meshes, Theoretical Computer Science, Vol. 197, pp. 57–77, Jan, 1998
  84. Atsuko Yamaguchi, Koji Nakano, and Satoru Miyano, An Approximation Algorithm for the Minimum Common Supertree Problem, Nordic Journal of Computing, Vol. 4, No. 3, 1997.
  85. Koji Nakano, and Stephan Olariu, An Optimal Algorithm for the Angle-Restricted All Nearest Neighbor Problem on the Reconfigurable Mesh, with Applications, IEEE Trans. on Parallel and Distributed Systems, Vol. 8, No. 9, pp. 983–990, Sept. 1997.
  86. Koji Nakano, Computing the Convex Hull of a Sorted Set of Points on a Reconfigurable Mesh, Parallel Algorithms and Applications, Vol.8, 243–250, 1996.
  87. Koji Nakano, Prefix-sums Algorithms on Reconfigurable Meshes, Parallel Processing Letters, 5, 1, 23–35, 1995.
  88. Koji Nakano, Optimal Initializing Algorithms for a Reconfigurable Mesh, Journal of Parallel and Distributed Computing, 24, 218–223, Jan, 1995.
  89. Wei Chen, Koji Nakano, Toshimitsu Masuzawa and Nobuki Tokura, A Parallel Method for Computing the Prefix Convex Hulls Problem, IEICE on Fundamentals of Electronics, Communications and Computer Science, J77-A, 10, pp. 1675–1683, Oct.,1994
  90. Koji Nakano, An Efficient Algorithm for Summing up Binary Values on a Reconfigurable Mesh, IEICE Trans. Fundamentals, Vol. E77-A, No. 4, pp. 652–657, Apr.,1994
  91. Koji Nakano, Optimal Sorting Algorithms on Bus-connected Processor Arrays, IEICE Trans. Fundamentals, Vol. E76-A, No. 11, pp. 2008-2015, Nov.,1993
  92. Koji Nakano, Toshimitsu Masuzawa and Nobuki Tokura, Distributed Leader Election on Chordal Ring Networks, IEICE Trans. Inf. and Syst. ,E75–D, 1 pp.58–63, Jan.,1992
  93. Koji Nakano, Toshimitsu Masuzawa and Nobuki Tokura, A Sub-logarithmic Time Sorting Algorithm on a Reconfigurable Array IEICE Trans. E–74, 11, pp.3894–3901, Nov.,1991

International Conferences

  1. Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, Ryota Yasudo: Folded Bloom Filter for High Bandwidth Memory, with GPU Implementations. CANDAR 2019: 18-27
  2. Daisuke Takafuji, Koji Nakano, Yasuaki Ito: Efficient GPU Implementations to Compute the Diameter of a Graph. CANDAR 2019: 102-111
  3. Hiroshi Kagawa, Yasuaki Ito, Koji Nakano: Throughput-Optimal Hardware Implementation of LZW Decompression on the FPGA. CANDAR Workshops 2019: 78-83
  4. Naoki Matsumura, Yasuaki Ito, Koji Nakano, Akihiko Kasagi, Tsuguchika Tabaru: Structured Sparse Fully-Connected Layers in the CNNs and Its GPU Acceleration, CANDAR Workshops 2019: 148-154
  5. Ryota Yasudo, Koji Nakano: The Degree Diameter Problem for Host-Switch Graphs, CANDAR Workshops 2019: 249-255
  6. Hisaki Yamane, Yasuaki Ito, Koji Nakano: A Watercolor Painting Image Generation Using Stroke-Based Rendering, CANDAR Workshops 2019: 265-469
  7. Koji Nakano, Yasuaki Ito, Jacir Luiz Bordim, FIFO-Based Hardware Sorters for High Bandwidth Memory. IPDPS Workshops 2019: 663-672 (PDF)
  8. Hironobu Kobayashi, Yasuaki Ito, Koji Nakano, Stained Glass Image Generation Using Voronoi Diagram and Its GPU Acceleration, PPAM 2019: 396-407
  9. Takahiro Inoue, Hiroki Tokura, Koji Nakano, Yasuaki Ito: Efficient Triangular Matrix Vector Multiplication on the GPU, PPAM 2019: 493-504
  10. Shunsuke Suita, Takahiro Nishimura, Hiroki Tokura, Koji Nakano, Yasuaki Ito, Akihiko Kasagi, Tsuguchika Tabaru: Efficient cuDNN-Compatible Convolution-Pooling on the GPU, PPAM 2019: 46-58
  11. Takuma Wada, Naoki Matsumura, Koji Nakano, Yasuaki Ito: Efficient Byte Stream Pattern Test using Bloom Filter with Rolling Hash Functions on the FPGA. CANDAR 2018: 66-75 (PDF)
  12. Lucas Saad N. Nunes, Jacir Luiz Bordim, Yasuaki Ito, Koji Nakano:　A Prefix-Sum-Based Rabin-Karp Implementation for Multiple Pattern Matching on GPGPU. CANDAR 2018: 139-145
  13. Naoki Matsumura, Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, Koji Nakano: Tile Art Image Generation Using Conditional Generative Adversarial Networks. CANDAR Workshops 2018: 209-215
  14. Yutaro Emoto, Shunji Funasaka, Hiroki Tokura, Takumi Honda, Koji Nakano and Yasuaki Ito, An Optimal Parallel Algorithm for Computing the Summed Area Table on the GPU, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 763–772, May 2018 (PDF).
  15. Shunji Funasaka, Koji Nakano, and Yasuaki Ito, Single Kernel Soft Synchronization Technique for Task Arrays on CUDA-enabled GPUs, with Applications, Proc. International Symposium on Computing and Networking, pp.11-20, Nov. 2017 (PDF).
  16. Hiroki Tokura, Yuki Kuroda, Yasuaki Ito, and Koji Nakano, A Square Pointillism Image Generation, and Its GPU Acceleration, Proc. International Symposium on Computing and Networking, pp. 38-47, Nov. 2017. (PDF)
  17. A Hybrid Architecture for the Approximate String Matching on an FPGA,Takuma Wada, Shunji Funasaka, Koji Nakano, and Yasuaki Ito, Proc. International Symposium on Computing and Networking, pp. 48-57, Nov. 2017 (PDF).
  18. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano, Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks, Proc. of International Parallel Processing Symposium, pp. 322-331, Aug. 2017.
  19. Takumi Honda, Shinnosuke Yamamoto, Hiroaki Honda, Koji Nakano, Yasuaki Ito, Simple and Fast Parallel Algorithms for the Voronoi Map and the Euclidean Distance Map, with GPU Implementations. Proc. of International Conference on Parallel Processing, pp.362-371, Aug. 2017 (PDF).
  20. Takahiro Nishimura, Jacir L. Bordim, Yasuaki Ito, and Koji Nakano, Accelerating the Smith-Waterman Algorithm Using Bitwise Parallel Bulk Computation Technique on GPU, Proc. of International Symposium on Parallel and Distributed Processing Systems Workshops, pp. 932-941, May 2017. (PDF)
  21. Yi Yang, Yasuaki Ito, Koji Nakano, Photomosaic Generation by Rearranging Subimages, with GPU Acceleration, Proc. of International Symposium on Parallel and Distributed Processing Systems Workshops, pp. 942-951, May 2017. (PDF)
  22. Shunji Funasaka, Koji Nakano and Yasuaki Ito, Light Loss-Less Data Compression, with GPU implementation, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 10048), pp. 281–294, December 2016 (PDF).
  23. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of LZW Compression in the FPGA, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 10048), pp. 512–520, December 2016. (PDF)
  24. Satoshi Fujita , Koji Nakano, Michihiro Koibuchi, Ikki Fujiwara, Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length, Proc. of the 16th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 10048), pp. 295-309, December 2016.
  25. Ryouhei Murooka, Yasuaki Ito and Koji Nakano, Accelerating Ant Colony Optimization for the Vertex Coloring Problem on the GPU, Proc. of International Symposium on Computing and Networking (CANDAR), 496–475, November 2016. (PDF)
  26. Lucas Saad, Jacir Bordim, Yasuaki Ito and Koji Nakano, A Memory-Access-Efficient Implementation of the Approximate String Matching Algorithm on GPU, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 483–489, November 2016.
  27. Naoaki Harada, Koji Nakano and Yasuaki Ito, A hardware sorter for almost sorted sequences, with FPGA implementations, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 565–571, November 2016 (PDF).
  28. Hiroki Tokura, Takumi Honda, Yasuaki Ito, Koji Nakano, Mitsuya Nishino, Yushiro Hirota and Masami Saeki, GPU-Accelerated Bulk Computation of the Eigenvalue Problem for Many Small Real Non-symmetric Matrices, Proc. of International Symposium on Computing and Networking (CANDAR), pp. 490–496, November 2016. (PDF)
  29. Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi: Randomly Optimized Grid Graph for Low-Latency Interconnection Networks, pp. 340-349, Proc. of International Conference on Parallel Processing (ICPP) 2016. (PDF)
  30. Toru Fujita, Koji Nakano, Yasuaki Ito, Bitwise Parallel Bulk Computation on the GPU, with Application to the CKY Parsing for Context-Free Grammars, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 589-598, May, 2016 (PDF).
  31. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of LZW Decompression in the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 599-607, May, 2016 (PDF).
  32. Shunji Funasaka, Koji Nakano, Yasuaki Ito, A Parallel Algorithm for LZW Decompression, with GPU Implementation, Proc. of International Conference on Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 228-237,2015 (PDF).
  33. Xin Zhou, Koji Nakano, and Yasuaki Ito, Parallel FDFM Approach for Computing GCDs Using the FPGA, Proc. of International Conference on Parallel Processing and Applied Mathematics (PPAM 2015, LNCS 9573), pp. 238-247, 2015 (PDF).
  34. Toru Fujita, Daigo Nishikori, Koji Nakano, Yasuaki Ito, Efficient GPU implementations for the Conway's Game of Life, Proc. International Symposium on Computing and Networking, pp. 11–20, December 2015(PDF).
  35. Tatsuya Kawamoto, Yasuaki Ito, Koji Nakano, A flexible-length-arithmetic processor based on FDFM approach in FPGAs, Proc. of International Symposium on Computing and Networking, pp. 364–370, December 2015(PDF).
  36. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallelization Techniques for Error Diffusion with GPU Implementations, Proc. of International Symposium on Computing and Networking, pp. 30–39, December 2015 (PDF).
  37. Lucas Saad, Jacir Bordim, Koji Nakano, Yasuaki Ito, A Fast Approximate String Matching Algorithm on GPU, Proc. International Symposium on Computing and Networking, pp. 188–192, December 2015.
  38. Takumi Honda, Yasuaki Ito, Koji Nakano, A Warp-synchronous Implementation for Multiple-length Multiplication on the GPU, Proc. of International Symposium on Computing and Networking, pp. 96–102, December 2015(PDF).
  39. Shunji Funasaka, Koji Nakano, Yasuaki Ito, Fast LZW compression using a GPU, Proc. of International Symposium on Computing and Networking, pp. 303–308, December 2015 (PDF).
  40. Hiroaki Kouge, Yasuaki Ito, Koji Nakano, GPU-Accelerated Digital Halftoning by the Local Exhaustive Search, Proc.of International Symposium on Parallel and Distributed Computing, pp. 82–87, June 2015. (PDF)
  41. Naoyuki Matsumoto, Koji Nakano, Yasuaki Ito, Optimal Parallel Hardware K-Sorter and Top K-Sorter, with FPGA implementations, Proc. of International Symposium on Parallel and Distributed Computing, pp. 138–147, June 2015. (PDF)
  42. Toru Fujita, Koji Nakano and Yasuaki Ito, Bulk GCD Computation Using a GPU to Break Weak RSA Keys, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 385–394, May 2015.(PDF)
  43. Lucas Rodrigues Costa, Lucas Saad N. Nunes, Jacir Luiz Bordim, Koji Nakano, Asterisk PBX Capacity Evaluation, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 519–524, May 2015.(PDF)
  44. Koji Nakano and Yasuaki Ito, Optimality of Fundamental Parallel Algorithms on the Hierarchical Memory Machine, with GPU implementation, Proc. of International Conference on Parallel, Distributed and Network-Based Processing, pp.626-634. March 2015 (PDF)
  45. Koji Nakano, A Time Optimal Parallel Algorithm for the Dynamic Programming on the Hierarchical Memory Machine, Proc. of International Symposium on Computing and Networking, pp. 86–95, Dec, 2014. (PDF)
  46. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA, Proc. of International Symposium on Computing and Networking, pp.447-452, Dec, 2014. (PDF)
  47. Satoshi Okamoto, Yasuaki Ito, Koji Nakano, Jacir L. Bordim, Thorough Evaluation of GPU Shared Memory Load and Store Instructions, Proc. of International Symposium on Computing and Networking, pp. 614–616, Dec, 2014. (PDF)
  48. Akihiko Kasagi, Koji Nakano, Yasuaki Ito, Parallel Algorithms for the Summed Area Table on the Asynchronous Hierarchical Memory Machine, with GPU implementations, Proc. of International Conference on Parallel Processing, pp.251-260, Sept. 2014. (PDF)
  49. Koji Nakano, Susumu Matsumae, Yasuaki Ito, Random Address Permute Shift Technique for the Shared Memory on GPUs, , Proc. of International Conference on Parallel Processing Workshops, pp. 429-438, Sept. 2014.(PDF)
  50. Hiroaki Kouge, Yasuaki Ito and Koji Nakano, A GPU Implementation of Clipping-Free Halftoning using the Direct Binary Search, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8630), pp. 57–70, August 2014. (PDF)
  51. Takumi Honda, Yasuaki Ito and Koji Nakano, GPU-accelerated Verification of the Collatz Conjecture, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 8630), pp. 483–496, August 2014. (PDF)
  52. Daisuke Takafuji, Koji Nakano and Yasuaki Ito, C2CU : A CUDA C Program Generator for Bulk Execution of a Sequential Algorithm, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP LNCS 8631), pp. 178–191, August 2014. (PDF)
  53. Xin Zhou, Yasuaki Ito, Koji Nakano, An Efficient Implementation of the Gradient-based Hough Transform using DSP slices and block RAMs on the FPGA, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 762–770, May 2014 (PDF).
  54. Kazuya Tani, Daisuke Takafuji, Koji Nakano, Yasuaki Ito, Bulk Execution of Oblivious Algorithms on the Unified Memory Machine, with GPU Implementation, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 586–595, May 2014 (PDF).
  55. Koji Nakano, Susumu Matsumae, The Super Warp Architecture with Random Address Shift, in Proc. of International Conference on High Performance Computing, pp. 256 - 265, Dec. 2013, (PDF).
  56. Koji Nakano, Susumu Matsumae and Yasuaki Ito, The Random Address Shift to Reduce the Memory Access Congestion on the Discrete Memory Machine, in Proc. of International Symposium on Computing and Networking, pp. 95–103, Dec. 2013, (PDF).
  57. Koji Nakano, Sequential Memory Access on the Unified Memory Machine with Application to the Dynamic Programming, in Proc. of International Symposium on Computing and Networking, pp. 85–94, Dec. 2013 (PDF).
  58. Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano and Yasuaki Ito, A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs, in Proc. of International Symposium on Computing and Networking, pp. 75–84, Dec. 2013, (PDF).
  59. Yuji Takeuchi, Daisuke Takafuji, Yasuaki Ito and Koji Nakano, ASCII Art Generation using the Local Exhaustive Search on the GPU, in Proc. of International Symposium on Computing and Networking, pp. 194–200, Dec. 2013, (PDF).
  60. Kaoru Hashimoto, Yasuaki Ito and Koji Nakano, Template Matching using DSP slices on the FPGA, in Proc. of International Symposium on Computing and Networking, pp. 338-344, Dec. 2013, (PDF).
  61. Ryosuke Nakamura, Yasuaki Ito and Koji Nakano, TinyCSE: Tiny Computer System for Education, in Proc. of International Symposium on Computing and Networking, pp. 639–641, Dec. 2013, (PDF).
  62. Akihiko Kasagi, Koji Nakano, and Yasuaki Ito, An Optimal Offline Permutation Algorithm on the Hierarchical Memory Machine, with the GPU implementation, Proc. of Int'l Conference on Parallel Processing, pp. 1–10, October, 2013, (PDF).
  63. Duhu Man, Koji Nakano and Yasuaki Ito, The Approximate String Matching on the Hierarchical Memory Machine, with Performance Evaluation, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 79–84, September 2013, ( PDF) .
  64. Xin Zhou, Yasuaki Ito and Koji Nakano, An Efficient Implementation of the Hough Transform using DSP slices and block RAMs on the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 85–90, September 2013, (PDF).
  65. Yuki Ago, Koji Nakano and Yasuaki Ito, A Classification Processor for a Support Vector Machine with embedded DSP slices and block RAMs in the FPGA, in Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC), pp. 91–96, September 2013, (PDF).
  66. Koji Nakano, The Hierarchical Memory Machine Model for GPUs, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 591–600, May 2013,　(PDF).
  67. Xin Zhou, Norihiro Tomagou, Yasuaki Ito, and Koji Nakano, Efficient Hough Transform on the FPGA using DPS slices and Block RAMs, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp.771-778, May 2013, (PDF).
  68. Akihiro Uchida, Yasuaki Ito and Koji Nakano, An Efficient GPU Implementation of Ant Colony Optimization for the Traveling Salesman Problem, Proc. of International Conference on Networking and Computing (ICNC), pp. 94–102, December 2012(PDF).
  69. Koji Nakano, Asynchronous Memory Machine Models with Barrier Synchronization, Proc. of International Conference on Networking and Computing (ICNC), pp. 58–67, December 2012(PDF).
  70. Koji Nakano, Efficient Implementations of the Approximate String Matching on the Memory Machine Models, Proc. of International Conference on Networking and Computing (ICNC), pp. 233–239, December 2012(PDF).
  71. Akihiko Kasagi, Koji Nakano and Yasuaki Ito, An Implementation of Conflict-Free Offline Permutation on the GPU, Proc. of International Conference on Networking and Computing (ICNC), pp. 226–232, December 2012(PDF).
  72. Kazufumi Nishida, Koji Nakano, Yasuaki Ito, Accelerating the Dynamic Programming for the Optial Poygon Triangulation on the GPU, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 7439), pp. 1-15, Sept, 2012. (PDF)
  73. Koji Nakano, An Optimal Prefix-sums Algorithms on the Memory Machine Models for GPUs, Proc. of International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP, LNCS 7439), pp. 99-113, Sept, 2012. (PDF)
  74. Koji Nakano, Simple Memory Machine Models for GPUs, Proc. of International Parallel and Distributed Processing Symposium Workshops, pp. 788-797, May 2012.(PDF)
  75. Duhu Man, Kenji Uda, Yasuaki Ito, and Koji Nakano, A GPU Implementation of Computing Euclidean Distance Map with Efficient Memory Access, Proc. of International Conference on Networking and Computing (ICNC), pp. 68–76, December 2011. (PDF)
  76. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles, Proc. of International Conference on Networking and Computing, pp. 77–86, December 2011. (PDF)
  77. Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito, The Parallel FDFM Processor Core Approach for Neural Networks, Proc. of International Conference on Networking and Computing, pp. 113–119, December 2011. (PDF)
  78. Akihiro Uchida, Yasuaki Ito, and Koji Nakano, Fast and Accurate Template Matching using Pixel Rearrangement on the GPU, Proc. of International Conference on Networking and Computing, pp. 153–159, December 2011. (PDF)
  79. Yasuaki Ito, Kouhei Ogawa, and Koji Nakano, Fast Ellipse Detection Algorithm using Hough Transform on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors, pp. 313–319, December 2011. (PDF)
  80. Kazufumi Nishida, Yasuaki Ito, and Koji Nakano, Accelerating the Dynamic Programming for the Matrix Chain Product on the GPU, Proc. of International Workshop on Challenges on Massively Parallel Processors, pp. 320–326, December 2011. (PDF)
  81. Bo Song, Yasuaki Ito, and Koji Nakano, CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models, pp. 532-541, May 2011. (PDF)
  82. Ian McLoughlin and Koji Nakano, A Perspective on the Experiential Learning of Computer Architecture, Proc. IEEE/ACM Int'l Conference on Cyber, Physical and Social Computing (CPSCom), pp. 868 - 872, Dec 2010.
  83. Duhu Man, Kenji Uda, Hironobu Ueyama, Yasuaki Ito, and Koji Nakano, Implementations of Parallel Computation of Euclidean Distance Map in Multicore Processors and GPUs, Proc. of International Conference on Networking and Computing, pp.120-127, Nov. 2010. (PDF)
  84. Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito, An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA, Proc. of International Conference on Networking and Computing, pp.140-147, Nov. 2010. (PDF)
  85. Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito, A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits, Proc. of International Conference on Networking and Computing, pp.148-157, Nov. 2010. (PDF)
  86. Kohei Ogawa, Yasuaki Ito, and Koji Nakano, Efficient Canny Edge Detection Using a GPU, Proc. of International Conference on Networking and Computing, pp.279-280, Nov. 2010. (PDF)
  87. Yasuaki Ito, Koji Nakano, Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM), Apr, 2010.
  88. Hidemasa Nakai, Koji Nakano, Low Noise Color Error Diffusion using the 8-Color Planes, Proc. of International MultiConferene of Engineers and Computer Scientists 2010 (IMECS), pp. 1425-1430, March 2010.
  89. Hidemasa Nakai, Koji Nakano, Cluster-Dot Halftoning based on the Error Diffusion with no Directional Characteristic, Proc. of International MultiConference of Engineers and Computer Scientists 2010 (IMECS), 1436-1441, March 2010.
  90. Masaya Nakagawa, Duhu Man, Yasuaki Ito, Koji Nakano, A Simple Parallel Convex Hull Algorithm for Sorted Points and the Performance Evaluation for the Multicore Processors, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 506-511, Dec. 2009. (PDF)
  91. Duhu Man, Yasuaki Ito, Koji Nakano, An Efficient Parallel Sorting Compatible with the Standard Qsort. Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 512-517, Dec. 2009. (PDF)
  92. Yasuaki Ito, Koji Nakano, A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Cojecture, Proc. IEEE International Symposium on Parallel and Dsitributed Processing with Applications, pp.63-70, Aug. 2009.
  93. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, RSA encryption and decryption using the redundant number system on the FPGA, Proc. IEEE International Symposium on Parallel and Distributed Processing, pp. 1-8, May 2009. (PDF)
  94. Kimiharu Nishihata, Duhu Man, Yasuaki Ito, and Koji Nakano, Parallel Sampling Sorting on the Multicore Procesors, Proc. of the International Conference on Applications and Principles of Informatin Science(APIS), pp. 233-236, Jan 2009.
  95. Xia Zhuge, Koji Nakano, Direct Binary Seach Based Algorithm for Hiding an Image in Two Distinct Images, Proc. of the International Conference on Applications and Principles of Informatin Science(APIS), pp. 251-254, Jan 2009.
  96. FengWei An, Koji Nakano, An Architecture for Veryfing Collatz Conjecture using an FPGA, Proc. of the International Conference on Applications and Principles of Informatin Science(APIS), pp. 375-378, Jan 2009.
  97. Koji Shigemoto, Kensuke Kawakami, Koji Nakano, Accelerating Montgomery Modulo Multiplication for Redundant Radix-64k Number System on the FPGA using Dual-Port Block RAMs, Proc. of International Conference On Embedded and Ubiquitous Computing(EUC), Dec., 2008. (PDF)
  98. Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito, A Tiny Processing System for Education and Small Embedded Systems on the FPGAs, Proc. of Embedded Software Optimization (ESO), pp. 472-479, Dec., 2008. (PDF)
  99. Nicole Nagel, Ruzbeh Shokranian, Jacir Bordim, Koji Nakano, MAC Layer Misbehavior on Ad Hoc Networks, Proc. of Network Centric Ubiquitous Systems (NCUS), pp. pp. 538-542,Dec., 2008.
  100. Simone Chagas, Eber Cayo, Koji Nakano, Jacir Bordim, The Impact of Backup Routes on the Routing and Wavelength Assignment Problem, Proc. of Network Centric Ubiquitous Systems (NCUS), pp. 519-523, Dec., 2008.
  101. Koji Nakano, Yasuaki Ito Processor, Assembler, and Compiler Design Education using an FPGA Proc. of International Conference on Parallel and Distributed Systems (ICPADS), pp. 723-728, Dec., 2008. (PDF)
  102. Xia Zhuge and Koji Nakano An Error Diffusion Based Algorithm for Hiding an Image in Distinct Two Images, Proc of Internatinal Conference on Computer Science and Software Engineering(CSSE), pp. 684-687, Dec., 2008.
  103. Kensuke Kawakami, Koji Shigemoto, Koji Nakano, Redundant Radix-2^r Number System for Accelerating Arithmetic Operations on the FPGAs, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 370-377, Dec., 2008.
  104. Yasuaki Ito, Koji Nakano, Optimized Component Labeling Algorithm for using in Medium Sized FPGAs Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 171–176, Dec., 2008.
  105. Yasuaki Ito, Koji Nakano, Component Labeling for k-Concave Binary Images Using an FPGA, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM), Apr, 2008.
  106. Xia Zhuge, Yuki Hirano, Koji Nakano, A New Hybrid Multitoning Based on the Direct Binary Search, Proc. of International Multi Conference of Engineers and Computer Scientists, Vol. 1, pp.627-632, March 2008.
  107. Koji Nakano,Optimal Initialization for the 1-Dimensional Reconfigurable Mesh, Proc. of International Conference on Applications and Principles of Information Science, pp.322-325 Jan. 2008.
  108. Koji Nakano, Randomized Initialization on the 1-dimentional Reconfigurable Mesh, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp. 293-300, Dec, 2007.
  109. M. F. Caetano, A.L.F. Fialho, J.L.Bordim, C.D.Castanho, R.P.Jacobi, K.Nakano, Proteus: An Architecture for Adapting Web Page on Small-Screen Devices, Proc. of IFIP International Conference on Network and Parallel Computing, pp. 161-170, Sept, 2007.
  110. Yasuaki Ito and Koji Nakano, Cluster-dot Screening by Local Exhaustive Search with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computational Models(CD-ROM), March, 2007.
  111. J. L. Bordim, T. Hunziker, K. Nakano, Limiting the Effects of Deafness and Hidden Terminal Problems in Directional Communications, Proc. of International Symposium on Parallel and Distributed Processing and Application, 195–206, Dec., 2006.
  112. J. L. Bordim, Y. Ito, K. Nakano: Randomized Leader Election Protocols in Noisy Radio Networks with a Single Transceiver, Proc. of International Symposium on Parallel and Distributed Processing and Application, 246–256, Dec., 2006.
  113. Yasuaki Ito and Koji Nakano and Youhei Yamagishi, Efficient Hardware Algorithm for N Choose K Counters, Proc. of Workshop on Advances in Parallel and Distributed Computatinal Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2006.
  114. Jacir L. Bordim, T. Hunziker, Koji Nakano, Active Carrier Sensing and Packet Sending – An Alternative to Boost the Performance in Directional Communications, Proc. of Parallel and Distributed Computing, Applications and Technologies, pp. 274–278, Dec, 2005.
  115. Koji Nakano and Youhei Yamagishi, Implementations of Hardware n Choose k Counters, Proc. of IEEE International Midwest Symposium on Circuits and Systems(CD-ROM), April 2005.
  116. Y. Ito and K. Nakano,FM Screening by the Local Exhaustive Search, with Hardware Acceleration, Proc. of Workshop on Advances in Parallel and Distributed Computatinal Models (CD-ROM of International Parallel and Distributed Processing Symposium), April 2004.
  117. Jacir L. Bordim, Yasuaki Ito, Koji Nakano, Instance-Specific Solutoins to Accelerate the CKY parsing, Proc. of Internatinal Conference on Engineering of Reconfigurable Systems and Algorithms, pp. 72-78, June, 2003.
  118. Koji Nakano, Etsuko Takamichi, An Image Retrieval System Using FPGAs, Proc. of Asia and South Pacific Design Automation Conference, pp.370-373, Dec, 2002.
  119. Jacir L Bordim, Yasuaki Ito, Koji Nakano, Accelerating the CKY Parsing using FPGAs, Proc. of High Performance Computig (LNCS 2552), pp.41–51, Dec, 2002.
  120. Jacir L Bordim, Jiangtao Cui, Naohiro Ishii, and Koji Nakano, Randomized Time- and Energy-Optimal Routing in Single-Hop Single-Channel Radio Networks, Proc. of International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), pp.313-320, Sept, 2002.
  121. Koji Nakano, An Optimal Randomized Ranking Algorithm on the k-channel Broadcast Communication Model, International Conference on Parallel Processing (ICPP), pp. 493–500, Aug, 2002.
  122. Koji Nakano, Time and Energy Optimal List Ranking Algorithms on the k-Channel Broadcast Communication Model, International Computing and Combinatorics Conference (COCOON), pp. 269–278, Aug, 2002.
  123. Koji Nakano and Stephan Olariu A Survey on Leader Election Protocols for Radio Networks, Proc. International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN), pp. 71–76, May, 2002. (invited paper)
  124. Jacir L Bordim, Koji Nakano, Hong Shen, Sorting on Single-Channel Wireless Sensor Networks, Proc. International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN), pp. 153–158, May, 2002.
  125. Jacir L. Bordim, Jiangtao Cui, Naohiro Ishii, and Koji Nakano, Doubly-logarithmic energy-efficient initialization protocol for single-hop radio networks, Workhop on Advances in Parallel and Distributed Conputational Models, Apr. 2002.
  126. Koji Nakano and Stephan Olariu, Uniform Leader Election Protocols in Radio Networks Proc. of International Conference on Parallel Processing, pp. 240-249, Aug, 2001.
  127. Jiangtao Cui, Jacir L. Bordim, Koji Nakano, Naohiro Ishii Simple Randomized Broadcast Protocols for Multi-hop Packet Radio Networks, Proc. of ACIS 2nd International Conference on Software Engineering Artificial Intelligence, Networking and Parallel/Distributed Computing, 385–390, Aug, 2001.
  128. R. S. Bhuvaneswaran, Jacir L. Bordim, Jiangtao Cui, Naohiro Ishii, Koji Nakano, An Energy-efficient Initialization Protocol for Wireless Sensor Networks, Proc. of Workshop on Wireless Networks and Mobile Computing, 423–428, Aug, 2001.
  129. R. S. Bhuvaneswaran, Jacir L. Bordim, Jiangtao Cui, and Koji Nakano, Fundamental Protocols on Wireless Sensor Networks, Workhop on Advances in Parallel and Distributed Conputational Models, Apr. 2001.
  130. Koji Nakano and Stephan Olariu, Randomized Leader Election Protocols in Radio Networks with no Collision Detection, Proc. of International Symposium on Algorithms and Computation, pp.362–373, Dec 2000.
  131. Koji Nakano, Stephan Olariu, and Albert Y. Zomaya, Energy-Efficient Deterministic Routing Protocols in Radio Networks, Proc. of International Conference on Parallel Processing, pp. 181–188, Aug, 2000.
  132. Koji Nakano and Stephan Olariu, Energy-Efficient Initialization Protocols for Radio Networks with no Collision Detection, Proc. of International Conference on Parallel Processing, pp 263–270, Aug. 2000.
  133. Koji Nakano and Stephan Olariu, Energy-Efficient Randomized Routing in Radio Networks, Proc. of 4th Workshop on Discrete Algorithms and Methods for Mobile Computing and Communications (DIALM), pp. 35–44, Aug. 2000.
  134. Koji Nakano and Stephan Olariu, Randomized Leader Election Protocols for Ad-hoc Networks, Proc. of 7th International Colloquium on Structural Information & Communication Complexity (Scirocco), pp. 253–267, June, 2000.
  135. Jiangtao Cui, Jacir L. Bordim, Koji Nakano, Tatsuya Hayashi, Naohiro Ishii, Multithreaded Parallel Computer Model with Performance Evaluation, Workhop on Advances in Parallel and Distributed Conputational Models, (LNCS 1800), pp.155-160, May 2000.
  136. Jacir L. Bordim, JiangtaoCui, Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Energy-Efficient Initialization Protocols for Ad-hoc Radio Networks, Proc. International Symposium on Algorithms and Computation, pp. 215–224, Dec 1999.
  137. Jacir L. Bordim, Tomoo Watanabe, Koji Nakano, and Tatsuya Hayashi, A tool for Algorithm Visualization on the Reconfigurable Mesh, Workshop on Advances in Parallel Computational Models, (Proc. of International Symposium on Parallel Architectures, Algorithms and Networks), pp.406–411, June, 1999.
  138. Koji Nakano, Stephan Olariu, and Albert Zomaya, A Time-Optimal Solution for the Path Cover Problems on Cographs, Proc. IEEE 13th International Parallel Processing Symposium, pp. 26–30, Apr. 1999.
  139. Rong Lin, Koji Nakano, Stephan Olariu, and Albert Zomaya, An Efficient VLSI Architecure Parallel Prefix Counting with Domino Logic, Proc. IEEE 13th International Parallel Processing Symposium, pp. 273–277, Apr. 1999.
  140. Tatsuya Hayashi, Koji Nakano, Stephan Olariu, Randomized Initialization Protocols for Packet Radio Networks, Proc. IEEE 13th International Parallel Processing Symposium, pp. 544–548, Apr. 1999.
  141. Rong Lin, Koji Nakano, Stephan Olariu, M. C. Pinotti, James L. Schwing, and Albert Y. Zomaya, Scalable Hardware-Algorithms for Binary Prefix Sums, Proc. of Reconfigurable Architecture Workshop (LNCS 1586), pp. 634–642, Apr. 1999.
  142. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, An O((log log n)^2) Time Convex Hull Algorithm on Reconfigurable Meshes, Proc. IEEE 12th International Parallel Processing Symposium, pp.439–446, Apr. 1998.
  143. Koji Nakano, and Stephan Olariu, Randomized $O(\log\log n)$-Round Leader Election Protocols in Packet Radio Networks, Proc. 8th International Symposium on Algorithms and Computation, pp.209–218 Dec. 1998.
  144. Koji Nakano, Stephan Olariu, James L. Schwing, Broadcast-Efficient Algorithms on the Coarse-Grain Broadcast Communication Model with Few Channels, Proc. IEEE 12th International Parallel Processing Symposium, pp. 31–35, Apr. 1998.
  145. R. Lin, Koji Nakano, Stephan Olariu, M.C. Pinotti, James L. Schwing, and Albert Y. Zomaya A Scalable VLSI Architecture for Binary Prefix Sums, Proc. IEEE 12th International Parallel Processing Symposium, pp.333–337, Apr. 1998.
  146. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Weighted and Unweighted Selection Algorithms for k Sorted Sequences, Proc. 8th International Symposium on Algorithms and Computation, pp, 52–51, Dec, 1997.
  147. Valery Viatkin, Koji Nakano, Tatsuya Hayashi, G, Ivanov, Event-Oriented Parallel Logic Computations for Distributed Real-Time Control Systems, Proc. 9th IASTED International Conference Parallel and Distributed Computing and Systems, pp. 553–558, Oct, 1997.
  148. Koji Nakano, Stephan Olariu, James L. Schwing, Broadcast-Efficient Sorting in the Presence of Few Channels, Proc. International Conference on Parallel Processing, pp.12–15, Aug, 1997.
  149. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Optimal Parallel Algorithms for Proximate Points, with Applications, Proc. 5th Internatioinal Workshop on Algorithms and Data Structures (LNCS 1272), pp. 224–233, Aug, 1997.
  150. Valery Viatkin, Koji Nakano, Tatsuya Hayashi, Optimized Processing of Complex Events in Discrete Control Systems using Binary Decision Diagrams Proc. 5th IFAC Workshop on Algorithms and Architectures for Real-Time Control, pp. 445–450, Apr, 1997.
  151. Tatsuya Hayashi, Koji Nakano, and Stephan Olariu, Work-Time Optimal k-merge Algorithms on the PRAM , Proc. IEEE 11th International Parallel Processing Symposium, pp. 298–302, Apr, 1997.
  152. Tatsya Hayashi, Koji Nakano, and Stephan Olariu, Efficient List Ranking on the Reconfigurable Mesh, with Applications, Proc. the 7th International Symposium on Algorithms and Computation (LNCS 1178), pp. 326–335, Dec, 1996.
  153. Valery Viatkin, Koji Nakano, Tatsuya Hayashi, Evaluation of Logic Expressions based on Event-oriented Interpretation of Marked Functional Diagrams, Proc. 35th Conference of Society for instrumentation and control engineering of Japan, pp. 1243-1248, 1996.
  154. Koji Nakano, and Stephan Olariu, An Efficient Algorithm for Row Minima Computations on Basic Reconfigurable Meshes Proc. International Conference on Parallel Processing, Vol. II, pp.54-61, 1996.
  155. Koji Nakano, and Stephan Olariu, An Optimal Algorithm for the Angle-Restricted All Nearest Neighbor Problem on the Reconfigurable Mesh, Proc. 10th International Parallel Processing Symposium, pp.687–691, Apr, 1996.
  156. Koji Nakano, and Koichi Wada, Integer Summing Algorithms on Reconfigurable Meshes, International Conference on Algorithms and Architectures for Parallel Processing, 1, pp. 187–196, Apr, 1995.
  157. Koji Nakano, Efficient Summing Algorithms on Reconfigurable Meshes, First Reconfigurable Architecture Workshop (IPPS 94) Apr, 1994.
  158. Koji Nakano, Linear Layouts of Generalized Hypercubes, 19th International Workshop on Graph-Theoretic Concepts in Computer Science (LNCS 790), pp.364–375, June, 1993.
 
en/publication.txt · 最終更新: 2013/01/22 09:36 by yasuaki
 
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